ICECS 2010 First Order Noise Shaping Time-to-Digital Converter Francesco Brandonisio, Prof. M. P. Kennedy and Prof. F. Maloberti (University of Pavia, Italy) 12th Dec. 2010 Department of Microelectronic Engineering, University College Cork and Tyndall National Institute, Ireland 1/21

• Application: All-Digital PLLs (ADPLLs). Motivations • Goal: Increase the resolution of a TDC by means of noise shaping of the quantization error. • Application: All-Digital PLLs (ADPLLs). Why first order noise shaping TDCs? As we will see in this presentation, first order noise shaping of the quantization error can be used to increase the resolution of a TDC. The final application is increasing the phase noise performance of All-Digital PLLs that include noise shaping TDCs. 2/21

Table of contents • Architectures of ADPLLs and Time-to-Digital Converters (TDC). • State of Art: Gated Ring Oscillator based TDC (GRO TDC). • Our Architecture: Local Oscillator based TDC (LO TDC). • Theoretical work the LO TDC. • Simulink and Verilog-AMS models of TDCs. • Experimental setup and measurements. In particular in the next slides, I will start by introducing some architectures of ADPLLs and Time-to-Digital Converters. First we will see the state of art first order noise shaping TDCs namely the Gated Ring Oscillator based TDC. I will also introduce our first order noise shaping TDC, namely a local oscillator based TDC. Afterwards, I will show some theoretical results, together with simulations and experiments all related to the resolution of the LO TDC. 3/21

Traditional Phase Locked Loop (PLL) A PLL is a feedback system. The Input and output of the system are periodic signals. At steady state the frequency of the output signal is N times the frequency of the input signal. • Applications: frequency synthesizers, trasmitters and receivers for telecommunication systems. 4/21

TDC based ADPLL Phase measure Feedback loop • PFD, loop filter and VCO replaced by digital equivalents. • The TDC measures the phase error between the output signals of the reference oscillator and divider. An All Digital PLL is a PLL in which PFD, loop filter and VCO replaced by digital equivalents. We can separate ADPLLs in TDC based and Accumulator based. What you see here is a TDC based ADPLL. A TDC is used to measure the phase error. [1] C.M. Hsu, Member, M. Z. Straayer, M. H. Perrott, “A Low-Noise Wide-BW 3.6-GHz Digital ∆Σ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation,” IEEE J. Solid-State Circ., vol. 43, no. 12, pp. 2776-2786, Dec. 2008. 5/21

Phase accumulator based ADPLL • The phase error is generated by means of the difference between the reference and feedback phase signals. • Phase accumulators generate the phase signals directly. This is istead what we can call a Phase Accumulator based ADPLL. Here the TDC is used to measure only a part of the phase error. [2] R. B. Staszewski, P, T. Balsara , “Phase-Domain All-Digital Phase-Locked Loop,”IEEE trans. on circuits and systems-II: express briefs, vol. 52, no. 3, Mar. 2005. 6/21

Time-to-Digital Converter A time-to-digital converter is a particular type of analog-to-digital converter in which the analog quantitity that has to be measured is a time interval. The unknown time interval could be associated with the phase error in a PLL, as we have seen in the previous slides. Typically the unknown time interval is defined by the edges of two signals. The analog to digital conversion is done by counting how many reference time intervals are included in the unknown one. • A TDC uses a reference time interval to measure an unknown time interval. 7/21

Types of Reference Time Interval • Delay of a delay element: Delay-line based TDCs. • Period of an oscillator: Oscillator based TDCs We have two possible types of reference time interval. The reference time interval can be the delay of a delay element (in a delay line based TDC) or the period of an oscillator (in an oscillator based TDC). So far noise shaping has been implemented in oscillator based TDCs. 8/21

Quantization Noise in TDCs • A TDC introduces quantization noise resulting from the finite resolution (res). • The Signal-to-Noise Ratio is decreased. A TDC with finite resolution introduces quantization error. The quantization error decreases the signal-to-noise ratio. In order to deal with this problem we can implement first order noise shaping of the quantization error. Let's see how it works. 9/21

First Order Noise Shaping TDCs • First order noise shaping of the quantization noise improves the SNR With noise shaping we push the power of the quantization error to high frequency. If we remove the high frequency spectral components by means of a loop filter for example, the signal to noise ratio is increased. This is given knowledge. So at this stage there are two important questions: first, how do we implement noise shaping in a TDC and, second, what's the effect of the noise shaping on the resolution of a TDC? In order to answer to the first question I would like to focus your attention on the equation which relates output and input of a noise shaping TDC. Notice that the quantization error of the previous measurement is included in the current measurement. In order to do that we can use a GRO based TDC. 10/21

Gated Ring Oscillator TDC: concept In a GRO TDC, in order to include the quantization error of the previous measurement in the current one, the state of the oscillator at the beginning of the current measurement has to be equal to that of the previous measurement. With a Gated Ring Oscillator you can do that by stopping the oscillator and preserving the the state of the oscillator between two concecutive measurements. • Start and stop the oscillator. • You need to preserve the state of the oscillator. 11/21

Gated Ring Oscillator TDC: circuit Charge Redistribution: extra circuitry required • Noise shaping. • Multi-stage architecture: the reference time interval is the delay of a CMOS inverter. This is the architecture of a GRO TDC. Consider that the state of the GRO is related to charge at the output of the CMOS intvertes. In a real Gated Ring Oscillator you have to deal with charge redistribution which makes difficult to preserve the state of the oscillator bewteen two consecutive measurements. However, the effect of charge redistribution can be addressed with extra circuitry. [3] B. Helal, M. Straayer, M. Perrott, “A Low Jitter 1.6 GHz Multiplying DLL Utilizing a Scrambling Time-to-Digital Converter and Digital Correlation,” VLSI Symp. Dig. Tech. Papers, pp. 166-167, June 2007 12/21

Local Oscillator based TDC (our solution) The time interval that has to be mesured is the period of the input signal So we said "can we do a noise shaping TDC without a gated ring oscillator?" The answer is yes. Provided that you measure only consecutive time intervals, we can use a free running oscillator to implement noise shaping. In fact, in this case, the state of the oscillator at the beginning of the current measurement is equal to that of the previous measurement by continuity. • Consecutive time intervals. • The local oscillator keeps oscillating. [4] F. Brandonisio, F. Maloberti, “An All-Digital PLL with a First Order Noise Shaping Time-to-Digital Converter,” Proc. of the 2010 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 241-244 13/21

No Charge Redistribution LO TDC: Block Diagram No Charge Redistribution Single-stage LO TDC • No specific requirements for the architecture of the local oscillator. • Same equations of a GRO TDC! • Simple! Multi-stage LO TDC • Extra counters to increase the resolution. With a local oscillator based TDC we have no charge redistribution. Moreover there are no ... 14/21

The system "LO TDC + Filter" Assume the system "LO TDC plus moving average filter" For a constant input it is possible to demonstrate that: In order to answer to the question "how can we relate the noise shaping to the resolution of a TDC" we found that if you consider the system "first order noise shaping TDC plus moving average filter" you can work on the equations of the system to prove analytically that the resolution of the system is res' = res over the number of samples of the filter when the input is constant. 15/21

Simulation Models Verilog-AMS Simulink • Current Simulation Time • Embedded Matlab Functions • Triggered Subsystems • Custom models with "electrical" data types • Event detection functions • Simulation Clock Source Block • Current Simulation Time Quick data processing and testing Transistor Level Libraries In order to prove our analytical derivations we have done some simulations. I've been working with Simulink and Verilog-AMS. For behavioural model Simulink and Verilog-AMS are equivalent, provided that you you use the proper features of Simulink. With simulink you can process the simulation data and test you models quickly. However. With Verilog-AMS you can use transistor level libraries. So that's good to work with Simulink and Verilog-AMS. My models can be separated in Exact and More Realistic. In the Exact models I use analytical equations and events. In the More realsitic models I use Flip-Flop, counters, digital gates, oscillators and so on. Types of Models • Exact: analytical equations and events. • More Realistic: Flip-Flops, counters, digital gates, oscillators. 16/21

• The models are implementable on a Xilinx Virtex 5 Simulated Characteristics Input-output characteristics of the system "first order noise shaping plus filter" • The simulation results of our Verilog-AMS and Simulink models are identical. • The models are implementable on a Xilinx Virtex 5 Here, I reported some simulated input-output characteristics of the system "first order noise shaping plus filter". We can clearly see that the resolution increases when the number of samples of the moving average filter Navg increases. 17/21

LO TDC on FPGA • The frequency of the Local Oscillator is 1.91667 MHz • The moving average filter is implemented in Matlab We also wanted to check our work with some experiments. This is a preliminay implementation on FPGA of an LO TDC. The moving average filter is implemented in matlab and the local oscillator is running at about 1.9 MHz. However, on a Virtex 5 we can work at much higher frequency, for example hundreds of MHz. 18/21

• The Reference Period is equal to about 400 ns. Resolution of the System "LO TDC + filter" from Predictions, Simulations and Experiments • The Reference Period is equal to about 400 ns. • Good matching between analytical predictions, simulations and experiments. This is a comparison between the resolution of the system "LO TDC plus filter" from predictions, simulations and experiments. The resolution of the system "noise shaping TDC plus filter" can be 100 times higher than the nominal resolution of the simple quantizer in the noise shaping TDC. 19/21

Experimental Results: Spectrum • Good matching between simulated and measured spectra • All the largest amplitude tones are reproduced by the simulations. This is comparison between simulated and measured spectra. A side effect of the noise shaping are tones. But we can predict their position analytically or by means of simulations. This examples shows that there is a good matching between simulations and experiments and that our model can be used to predict the positions of the largest amplitude tones. 20/21

Conclusions • We introduced the architecture of the LO TDC. • We derived analytical equations to predict the resolution of the system "LO TDC plus moving average filter". • We developed Verilog AMS and Simulink models of our TDC. • We verified the analytical predictions and simulations related to the resolution of the the system "LO TDC plus moving average filter" with experimental measurements on Xilinx Virtex-5. • An ADPLL with an LO TDC on Virtex-5 is under development. And we are currently working towards the implementation of an ADPLL with an LO TDC on Virtex-5 21/21

References [1] C.M. Hsu, Member, M. Z. Straayer, M. H. Perrott, “A Low-Noise Wide-BW 3.6-GHz Digital ∆Σ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation,” IEEE J. Solid-State Circ., vol. 43, no. 12, pp. 2776-2786, Dec. 2008. [2] R. B. Staszewski, P, T. Balsara , “Phase-Domain All-Digital Phase-Locked Loop,”IEEE trans. on circuits and systems-II: express briefs, vol. 52, no. 3, Mar. 2005. [3] B. Helal, M. Straayer, M. Perrott, “A Low Jitter 1.6 GHz Multiplying DLL Utilizing a Scrambling Time-to-Digital Converter and Digital Correlation,” VLSI Symp. Dig. Tech. Papers, pp. 166-167, June 2007. [4] F. Brandonisio, F. Maloberti, “An All-Digital PLL with a First Order Noise Shaping Time-to-Digital Converter,” Proc. of the 2010 IEEE International Symposium on Circuits and Systems (ISCAS 2010), pp. 241-244. [5] F. Brandonisio, M. P. Kennedy, F. Maloberti, “First Order Noise Shaping Local-Oscillator Based Time-to-Digital Converter,” To be published on Proc. of the 17th IEEE International Conference on Electronics, Circuits, and Systems, (ICECS 2010).

Thanks to Science Foundation Ireland Acknoledgments Thanks to Science Foundation Ireland and to FIRB, Italian National Program, Project RBAP06L4S5. Thanks for listening!