1 Demo Link and the LOC Status Report 1.Demo Link status 2.LOC2 status 3.Irradiation tests on optical fiber 4.Summary Vitaliy for the SMU team

J. Ye, Dept. of Phys. Demo Link and LOC report at UCSC 2 Demo Link status The idea: Use the GOL to construct an optical link to read out the staves under development. Provide a Giga-bit optical link that develops together with the detector and front-end ASICs. Provide a test vehicle to study system and integration issues at an early stage. Demo Links can be quickly constructed with LOC or GBTx when they become available in 2009/2010. These demo links will lead a baseline design for final production, installation evaluations and will provide links for reliability studies before the production begins. The status: Next page. The plan:

J. Ye, Dept. of Phys. Demo Link and LOC report at UCSC 3 The status Block diagram. The interface boards can be changed with the stave development.

J. Ye, Dept. of Phys. Demo Link and LOC report at UCSC 4 The status Design and layout All documents (schematics, layouts) available online: The GOL and TLK carrier boards sent for fab.+assembly on 8/6. GOL carrier board TLK carrier board SFP+/VL GOL TLK

J. Ye, Dept. of Phys. Demo Link and LOC report at UCSC 5 The plan: Currently layout the two interface boards. FPGA code development when all boards are out for fabrication and assembly. 8/25 – 9/5: debugging at SMU. 9/10, 11: first test at LBNL. May need a few integration tests and modifications of the interface boards. Will provide boards to interested groups for system level studies by the end of this year.

J. Ye, Dept. of Phys. Demo Link and LOC report at UCSC 6 LOC2 status Design status: Currently carry out post layout simulations on key components to define the speed of LOC2. Still in discussion with people in Inner Detector and in LAr trying to make LOC2 best fit the needs in both readout. In ID, we need to work more closely with people who develop the (supper-) module-controller to understand the input to LOC2. We may make use of the fact that the output of MC is already 8B/10B encoded to maximize the use of the bandwidth. Current simulations show a 5 Gbps LOC2 hopeful. Details in the following pages. The plan: after the status report.

J. Ye, Dept. of Phys. Demo Link and LOC report at UCSC 7 LOC2 Block diagram and challenging spots: 16 bit Input register LVDS to LVCMOS 2:1 MUX to 8 bit 8B/10B Comma PRBS PLL + clks MUX Cntrl config Odd bits shift register Even bits shift register Latch CML driver 2:1 MUX Data Clk_ref Cntrl/Config 16 LVDS 10 bit Serial output to Versatile Link Critical components: 1.PLL. VCO, the first stage divider  speed. Architecture choice: reliability, jitter, implementation. 2.Static D-flip-flop. The building block of the divider, and the shift register  speed. 3.CML driver. Inverter: basic unit of a CMOS circuit. Study the PMOS/NMOS ratio, circuit speed. We may move the 8B/10B encoder out of LOC2 to better interface ID and LAr. That is, we may design dedicated interface chips for LOC’s applications. This is in discussion right now and will be finalized soon.

J. Ye, Dept. of Phys. Demo Link and LOC report at UCSC 8 The inverter PMOS/NMOS ratio adjusted to have the same 1  0 and 0  1 delays. The ratio: n*(1.9/1.4) where n = 1,2,3,4… Basic layout, multi-finer layout checked to optimize speed. The delay is about 32~35 ps (drive itself), corresponding to a frequency of about 30 GHz. Agree with Peregrine’s tech notes, and comparable with speeds achieved in 0.13 to 0.15 micron bulk CMOS technology. (We only use RN/RP transistor which have been tested. We may be able to use IN/IP transistors are faster, and may be comparable with 0.13um process.) schematics layout.

J. Ye, Dept. of Phys. Demo Link and LOC report at UCSC 9 The D-flip-flop (DFF) We started out with the C 2 MOS type of DFF used in GOL, but moved to the TGDFF: ~20% faster, and at least the same SEE immunity (Ramanarayanan, Upenn). Different transistor size, single finger and multi-finger layouts are checked. The total delay is 292 ps (slowest or the S-S corner). This indicates a 5 Gbps serializer possible, because the time needed for a basic unit (DFF+mux) is 400 ps. schematics Mostly single- finger layout multi-finger layout

J. Ye, Dept. of Phys. Demo Link and LOC report at UCSC 10 Differential Ring oscillator VCO We choose this 4-stage VCO, a similar structure as in the GOL. Schematic level simulation indicates that a maximum frequency of 5.5GHz can be reached (the typical-typical corner). We need 2.5 GHz from post layout for 5 Gbps data transmission with a 50% duty cycle.

J. Ye, Dept. of Phys. Demo Link and LOC report at UCSC 11 The divider in the first stage The first stage divider in the PLL provides the bit clock, loading clock to the serializing unit. This first stage has to run at 2.5 GHz for 5 Gbps data rate. A two-arm serializer requires a divid-by-5 first stage. This is challenging at 2.5 GHz and it is being studied. A (jitter improved) four-arm serializer requires a divid-by-2 first stage, which is a DFF + Inverter. Our TGDFF(292ps, S-S) + Inverter(35ps, T-T) leaves us a good margin to run at 2.5 GHz. But we prefer the two-arm serializer for its simplicity.

J. Ye, Dept. of Phys. Demo Link and LOC report at UCSC 12 LOC2 work plan, near future Finalize the structure: with 8B/10B encoder or move the encoder out. With the latter, dedicated interface chips will be designed to best cope with the input data and maximize the use of the link bandwidth. Post layout studies on all the critical components and understand the speed of LOC2. At this moment, 5 Gbps is hopeful. Careful studies on the PLL, mostly the RJ, or phase noise. A design review (1 st ), Oct./Nov. time frame, at BNL or CERN on the critical parts. Get help from the community on things we may have overlooked, misunderstand, etc.

J. Ye, Dept. of Phys. Demo Link and LOC report at UCSC 13 LOC2 work plan, till April 2009 After the 1 st design review, we will move on to Complete PLL and clock unit design. Complete the serializer design. Implement the 8B/10B and 64B/66B Encoders, or design the interface chips. Implement the control/config unit. Implement the CML driver. We aim for the 2 nd design review, Jan./Feb. 2009, on the whole chip or chip set. We aim for the April 09 submission, and the tests in lab July 09. We will provide demo-link and system design document for groups that are interested in using this chip in the fall of Full evaluation of LOC2, including irradiation tests are planned to take place in the fall of Reference: GBTx is planned to be available end of 2009.

J. Ye, Dept. of Phys. Demo Link and LOC report at UCSC 14 Irradiation tests on optical fiber To complete a rad-tol optical link system, one needs to identify rad-tol components such as VCSEL, fiber and PINs. This part of the work is now the Versatile Project. At SMU, we identified a 10G fiber and performed several tests on the fiber. The report here consists: Results from ATLAS LAr. Narrow down to Germanium doped GRIN fiber. Preliminary tests.

J. Ye, Dept. of Phys. Demo Link and LOC report at UCSC 15 Results from ATLAS LAr Ref: Nucl. Phys. B, Proc. Suppl. 78 (1999) Irradiation studies of multimode optical fibres for use in ATLAS front-end links POF: Plasma Optics Fiber, Germanium doped. From the production qualification tests: see next page.

J. Ye, Dept. of Phys. Demo Link and LOC report at UCSC 16 Results from ATLAS LAr From ATLAS LAr fiber selection: Germanium doped MM fiber from Plasma Optical Fibres have been found to withstand radiations over 800~Gy(Si) and 2 × cm -2 (1-MeV equivalent in Si) with less than 0.1~dB/m attenuation. The fiber batch used for the production of the optical cables was verified using a Co-60 source. Two 5 cm diameter rolls with 100~m of fiber each were irradiated with a dose rate of 150 Gy/hr. After 1 hour of irradiation the transmission loss over the 100 m was less than 10% or less than dB/m. Immediately after 2 hours irradiation (300 Gy) the loss was dB/m, but it improved to dB/1m within 10 minutes, indicating a fast annealing process was taking place. The optical loss was measured to be dB/m immediatly after the total dose reached 2.8 kGy. Within 1 hour annealing at room temperature, the loss was reduced to -0.1 dB/m, satisfying the requirement we set for radiation induced optical power loss. We expect the actual loss in real ATLAS environment is much less than -0.1 dB/m due to the fast annealing process. Because there are only a few meters of fiber that is actually at the FEB location, we estimate a maximum optical power loss due to radiation to be less than 1 dB, well within the 10 dB power margin we have.

J. Ye, Dept. of Phys. Demo Link and LOC report at UCSC 17 Narrow down to Germanium doped GRIN fiber Ref: IEEE Trans. On Nuclear Science, Vol. 54, No. 4, Aug. 2007, Low-Dose Radiation-Induces Attenuation at InfraRed Wavelengths for P-Doped, Ge-Doped and Pure Silica-Core Optical Fibers 850 nm 1300 nm

J. Ye, Dept. of Phys. Demo Link and LOC report at UCSC 18 Preliminary tests Gamma (Co-60) and Proton (230 MeV) tests Infinicor SX+ 50/250  m/1.6mm MM. 10G fiber from Corning. Germanium doped. Very small light loss at low flux (dose rate). Big loss at high flux but anneals very quickly (within 1 hour) back. Fiber under proton test

J. Ye, Dept. of Phys. Demo Link and LOC report at UCSC 19 Preliminary tests Co-60 at BNL, dose rate: 30 krad/hr. Fiber: Corning Infinicor SX+ 50/125 MM fiber, 45 m under irradiation. Total RIA: 0.04 dB/m after 1.4 Mrad. Annealing effects observed. More annealing results will follow once we get our equipment back to SMU. Run #Dose (krad) Accumulated dose (krad) fibre RIA (dB) Accumulated RIA (dB) Ref. fiber (dB) Accumulated ref. fiber (dB)

J. Ye, Dept. of Phys. Demo Link and LOC report at UCSC 20 Conclusion on fiber (preliminary) Corning Infinicor SX+ 50/125 MM fibers from different production batches, packaging companies were irradiated with gamma (Co-60) and proton (230 MeV). More tests with higher dose rate and total dose are to be carried out by Oxford group to reach 50 Mrads. Careful data analysis, especially on annealing effects, needs to be carried out. More tests, especially neutron or proton may be needed to study possible NIEL effect, or to confirm that the lack of it. Preliminary results indicate that this fiber may be suitable for ID upgrade.

J. Ye, Dept. of Phys. Demo Link and LOC report at UCSC 21 Summary The GOL based demo link will be constructed and put to use in Sept./Oct. time frame. This demo link will be used to perform many system level studies on the Giga-bit optical link. Demo links based on LOC or GBTx will follow. This exercise will lead to a baseline design for the upgrade of optical readout. The LOC2 design is on track for a user chip in It is hopeful to achieve 5 Gbps speed. We need to work more closely with upstream ASIC developers to define the interface. R&D work in the frame of Versatile Link project is on-going to identify components for a rad-tol optical link. At least one type of fiber (Corning Infinicor SX+ 50/125 MM ) has been tested with gamma and proton and the preliminary results indicate that this fiber may be suitable for the ID upgrade.

J. Ye, Dept. of Phys. Demo Link and LOC report at UCSC 22 Backup slides

J. Ye, Dept. of Phys. Demo Link and LOC report at UCSC 23 Block diagram The preliminary LOC2 block diagram 16 bit Input register LVDS to LVCMOS 2:1 MUX to 8 bit 8B/10B Comma PRBS PLL + clks MUX Cntrl config Odd bits shift register Even bits shift register Latch CML driver 2:1 MUX Data Clk_ref Cntrl/Config 16 LVDS 10 bit Serial output to Versatile Link Input Output LOCVL fiber Parallel data GBTxVL fiber Parallel data System implementation

J. Ye, Dept. of Phys. Demo Link and LOC report at UCSC 24 Design considerations Implement measures to address lessons learned from LOC1: period jitter from the serializer; control PLL RJ; output driver quality. Conservative circuit units (static D-flip-flop, majority voting) are used to reduce SEE cross section. We would like to take advantage of the Versatile Link development, and move the optical interface from LOC to VL. LOC2 should have the basic but complete functions as a “user” chip so that groups outside of SMU can use it to implement in their systems.

J. Ye, Dept. of Phys. Demo Link and LOC report at UCSC 25 Key features A Serializer at 3.2 Gbps, goal: push it up to 5 Gbps (ref. GBTx at 5 Gbps); Differential data input, 16 bit LVDS; Differential parallel data rate reference clock input; Data sampling at the rising or falling edge of the reference clock; Internal PRBS; Differential electrical output (CML), to be coupled to the Versatile Link input; Compatible with commercial GBE receivers (8B/10B encoder). The receiver can be FPGA based. This will greatly help in the demo-link and the ROD designs; Single 2.5 voltage power supply.