Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting The Front-End Driver Card FEDv1 VME crate requirements definition FEDv1 status : Hardware Firmware & low-level software FEDv1 testing plans

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Crates Requirements Document Requirements needed for Tracker Crate ordering Aim to have common VME64x bus crates for FED and FEC List of special needs, connectors, power…etc. E.g. FED may require Transition cards (DAQ links) References to LHC Crate technical specification EP document Released for comments

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Crates Requirements Document

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Overview VME-FPGA TTCrx BE-FPGA Event Builder Buffers FPGA Configuration Compact Flash Power DC-DC DAQ Interface 12 Front-End Modules x 8 Double-sided board CERN Opto- Rx Analogue/Digital 96 Tracker Opto Fibres VME Interface Xilinx Virtex-II FPGA Modularity 9U VME64x Form Factor Modularity matches Opto Links 8 x Front-End “modules” OptoRx/Digitisation/Cluster Finding Back-End module / Event Builder VME module / Configuration Power module Other Interfaces: TTC : Clk / L1 / BX DAQ : Fast Readout Link TCS : Busy & Throttle VME : Control & Monitoring JTAG : Test & Configuration FE-FPGA Cluster Finder TTC TCS Temp Monitor JTAG TCS : Trigger Control System 9U VME64x

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Project History VME-FPGA TTCrx BE-FPGA Event Builder Buffers FPGA Configuration Compact Flash Power DC-DC DAQ Interface 12 Front-End Modules x 8 Double-sided board CERN Opto- Rx Analogue/Digital 96 Tracker Opto Fibres VME Interface Xilinx Virtex-II FPGA Analogue Circuit for signal match from OptoRx to ADCs (good working relationship with Francois&Jan) Fit 96 ADC channels on board FPGAs choice of Xilinx Virtex-II family. Fitting FE design into target part. But progress (always) take longer than you think… S-LINK Transition card / Direct? Power & VME modules took more time than anticipated FPGA de-coupling schemes. + many minor design decisions. ~ 1Q behind schedule May 2002 FE-FPGA Cluster Finder TTC TCS Temp Monitor JTAG TCS : Trigger Control System 9U VME64x

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Board Layout Primary Side Complex board Pushing density limits Analogue & Digital & signal integrity

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FED v1 Board Layout Secondary Side View thru the board Double sided

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Overview 12 Front-End Modules x 8 Double-sided board CERN Opto- Rx Analogue/Digital 96 Tracker Opto Fibres Xilinx Virtex-II FPGA Modularity 8 x Front-End “modules” FE-FPGA Cluster Finder 9U VME64x

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Front-End module 12 Fibre Ribbon PD Array *5* CLK DCM LVDSCLK40 from TTC CERN Opto Rx 6 CLOCK CONTROL DATA DATA 160 MHz 3 N Full Partially Full RESET Cluster Finding FPGA Delay FPGA Delay FPGA Delay FPGA Dual ADC 10-bits 40 MHz OpAmp XC2V1500XC2V40AD9218EL2140 CLK 10 ASIC 4*4* Data Control Digital Processing 12x trim DAC Temp Sensor LM82 * Double Data Rate I/O Each individual ADC clock skew is adjustable in steps ~ 1nsec

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Front-End module Primary Routed Note: FPGA de-coupling OptoRx ADCs 40K FPGAs1500K FPGA OpAmps 12 optical channels Dense circuitry

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Front-End module Secondary Routed Double-sided

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Full-Scale 9U Layout TTCrx BE-FPGA Event Builder Buffers DAQ Interface 12 Front-End Modules x 8 Double-sided board CERN Opto- Rx Analogue/Digital 96 Tracker Opto Fibres Xilinx Virtex-II FPGA Back-End module For each L1-Trigger: Collects 8 x FE variable length data fragments Formats FED event for DAQ Appends TTC synch information Buffers in External QDR SRAM Sends data via DAQ Front-end Readout Link FRL Signals to TCS : Busy/Throttle FE-FPGA Cluster Finder TTC TCS TCS : Trigger Control System 9U VME64x PinDiode /Amp ASIC

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting DAQ Front-end Readout Link FRL DAQ Mezzanine Card Transition Card Busy Throttle S-LINK64 FEDv1 FED-DAQ Interface TTCrx BE-FPGA Event Builder Buffers 12 TTC TCS FRL DAQ links use S-LINK64 standard Implementation: Channel Link 800 MBytes/sec max Average DAQ rate 200 MBytes/sec Due to mechanical constraints place DAQ link card on Transition card

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting Alternative scheme: “Channel Link” in Virtex-II BE-FPGA DAQ FEDv1 FED-DAQ Interface (alternative) TTCrx BE-FPGA Event Builder Buffers 12 TTC TCS

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 VME module VME-FPGA FPGA Configuration 12 VME Interface Xilinx Virtex-II FPGA VME Interface Minimum Features for 2003: A32/D32 Slave access only Possible Slave BLT32? No DMA engine No Interrupts Possible 64x Dynamic Addressing? FPGA Configuration: Xilinx System ACE Compact Flash MPU-VME interface for in-situ re- programming via Crate Controller (Not in 2003?) JTAG for Configuration & Test JTAG 9U VME64x System ACE CF

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Power module Power DC-DC 12 Front-End Modules x 8 Double-sided board CERN Opto- Rx Analogue/Digital Xilinx Virtex-II FPGA Standard LHC spec crate supplies: +3.3V, +5V, +12V Derive: -5V, 1.5V, 2.5V on board Board Estimate ~ 80 W Hot Swap Controllers: Electronic fuses Protection against out of range voltage & current Sequence power Protections: Over temperature shutdown Temp Monitor TCS : Trigger Control System 9U VME64x Warning

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Hardware Status VME-FPGA TTCrx BE-FPGA Event Builder Buffers FPGA Configuration Power DC-DC DAQ Interface 12 Front-End Modules x 8 Double-sided board CERN Opto- Rx Analogue/Digital 96 Tracker Opto Fibres VME Interface Xilinx Virtex-II FPGA FE-FPGA Cluster Finder TTC TCS Temp Monitor JTAG TCS : Trigger Control System 9U VME64x Board Status

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FED Schedule Schedule 2002/Q4 : 2 x for UK test Batch 1* 2003/Q4 : ~10? x CERN Batch 2** 2004/Q4 : ~10? x FEDv2 manufacture 2005/Q2** : 500 x FEDv3 manufacture (**funds permitting) FEDv1 : Full scale Prototype FEDv2 : Pre-production FEDv3 : Final production FEDv1 FEDv2 FEDv3 * OptoRx added post-assembly. ** Procurement started for critical parts for Batch 2

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FED TIB Test Schedule Q. Deliver 2 x FEDv1 Batch CERN for TIB test starting July 2003 ?? Very tough. Testing is a big job. Can’t promise to deliver in June? Use Batch1 PCBs. ie No design iteration possible. Risk that design has major fault. Prioritise essential firmware and testing plan. Require explicit list of functionality essential for the TIB assembly centre. FEDv1 FEDv2 FEDv3 TIB? OptoRx?

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Firmware & Low-Level Software

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Firmware & Software VME-FPGA TTCrx BE-FPGA Event Builder Buffers FPGA Configuration Power DC-DC DAQ Interface 12 Front-End Modules x 8 Double-sided board CERN Opto- Rx Analogue/Digital 96 Tracker Opto Fibres VME Interface Xilinx Virtex-II FPGA Digital Processing Xilinx Virtex-II FPGAs 40K->3M gates 4 Species of FPGA: Delay FPGA 40K: Clock skew +... FE FPGA 1.5M: Cluster Finding +... BE FPGA 2M: Event Building +... VME FPGA 1M: VME Interface +... in general one designer per species FPGAs programmed in both VHDL & VERILOG FE-FPGA Cluster Finder TTC TCS Temp Monitor JTAG TCS : Trigger Control System 9U VME64x

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Front-End module 12 Fibre Ribbon PD Array *5* CLK DCM LVDSCLK40 from TTC CERN Opto Rx 6 CLOCK CONTROL DATA DATA 160 MHz 3 N Full Partially Full RESET Cluster Finding FPGA Delay FPGA Delay FPGA Delay FPGA Dual ADC 10-bits 40 MHz OpAmp XC2V1500XC2V40AD9218EL2140 CLK 10 ASIC 4*4* Data Control Digital Processing 12x trim DAC Temp Sensor LM82 * Double Data Rate I/O Each individual ADC clock skew is adjustable in steps ~ 1nsec

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting CMS Silicon Strip Tracker FED Front-End FPGA Logic ADC 1 10 sync 11 trig2 Ped sub 11 trig3 Re-order cm sub 8 Hit finding s-data s-addr8 16 hit Packetiser 4 averages 8 header control DPM 16 No hits Sequencer-mux 88 a d a d ADC trig1 sync 11 trig2 Ped sub 11 trig3 Re-order cm sub 8 Hit finding s-data s-addr cycles hit DPM 16 No hits Sequencer-mux 88 a d a d status averages 8 headerstatus nx256x16 trig4 Synch in Synch out Synch emulator in mux Serial I/O Serial Int B’Scan Local IO Config Cluster Finding FPGA VERILOG Firmware Full flags data Global reset Control Sub resets 10 Phase Registers Phase Registers 2 x 256 cycles256 cyclesnx256x16 trig1 Synch error 4x Temp Sensor Delay Line Opto Rx Clock 40 MHz DLL 1x 2x 4x per adc channel phase compensation required to bring data into step + Raw Data mode, Scope mode, Test modes MHz

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Full-Scale 9U Layout TTCrx BE-FPGA Event Builder Buffers DAQ Interface 12 Front-End Modules x 8 Double-sided board CERN Opto- Rx Analogue/Digital 96 Tracker Opto Fibres Xilinx Virtex-II FPGA Back-End module For each L1-Trigger: Collects 8 x FE variable length data fragments Formats FED event for DAQ Appends TTC synch information Buffers in External QDR SRAM Sends data via DAQ Front-end Readout Link FRL Signals to TCS : Busy/Throttle FE-FPGA Cluster Finder TTC TCS TCS : Trigger Control System 9U VME64x PinDiode /Amp ASIC

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Back-End FPGA Logic FIFO Circular Buffers Frame_Syncs Readout_Syncs Monitor_Syncs x8 TTC Rx TCS ‘VME’ DECODE CONTROL & MONITOR Data_stream 0 Data_stream Data In 20 Address 18 Data Out 64 FRL to DAQ SLINK64 64 R/W Address Generator APV hdrs Lengths Bx,Ex Em Hdr diagnostics Data 80 Mhz L1 100 kHz MHz 40 Mhz Clock40 Reset DCM x1 x2 x4 2 x QDR SRAM x2 burst BSCAN 160 MHz 80 MHz Lengths Header FF/PF Flags Control 2 MBytes VME copy path to local buffer

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Status VME-FPGA TTCrx BE-FPGA Event Builder Buffers FPGA Configuration Power DC-DC DAQ Interface 12 Front-End Modules x 8 Double-sided board CERN Opto- Rx Analogue/Digital 96 Tracker Opto Fibres VME Interface Xilinx Virtex-II FPGA FE-FPGA Cluster Finder TTC TCS Temp Monitor JTAG TCS : Trigger Control System 9U VME64x Board Status Design effort now re- directed to completing Firmware. Team is sufficient. Design is progressing well.

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Module Testing Firmware Functionality VME interface A32/D32 only Raw Data events only (unpacked) Scope mode for timing TTC interface ? Individual ADC clock skews Hardware trigger throttle ? S-LINK TCS interface Cluster Finding Firmware In-situ Firmware updates Auto-Calibration VME64x dynamic addressing Board hot swapping EssentialNon Essential Q. What event rate needed for testing? Q. What features? Do we need individual channel DAC offsets ? (or is common OptoRx offset sufficient) Note: Firmware is tested (simulation/dev boards) but “real world” often has surprises.

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Low-Level Software XDAQ Hardware Abstraction Layer we need to learn more but... fedlib C++ class API lowest level access structures & functions for user programs (object contained in fed class?) fedlib calls HAL read/write functions Hide details/sequences from user. int fedlib_load_fe_peds(fe_mod, struct peds,..) Maybe additional layer above fedlib? (see Costas’s talk) Assume PC Linux + HAL supported VME Interface card fedlib fed task user space

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Address Map Hidden from outside world… But need this before fedlib API Address Map under construction. Implementation tightly coupled to Firmware. Probably reserve < 1 MByte / FED FE FPGA #0 FE FPGA #1 FE FPGA #2 FE FPGA #3 FE FPGA #4 FE FPGA #5 FE FPGA #6 FE FPGA #7 FED local CSR TTCrx Event Memory FPGA confign Pedestals Skew values...etc

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Parameter Loading Mechanism of FED setup hidden from User e.g. Loading FED parameters not trivial Write constants e.g. Peds to small local FPGA buffer. Limited FPGA memory. Send command to load to FE FPGA FPGA “engine” handles serial commands Optional readback Repeat for next block reusing same parameter area Constraints: Can’t load individual channels NB can’t access constants during Run! Command & Status Parameter Load block Parameter Readback block under development

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Firmware & Software VME-FPGA TTCrx BE-FPGA Event Builder Buffers FPGA Configuration Power DC-DC DAQ Interface 12 Front-End Modules x 8 Double-sided board CERN Opto- Rx Analogue/Digital 96 Tracker Opto Fibres VME Interface Xilinx Virtex-II FPGA Digital Processing Flexible Digital Logic: Xilinx Virtex-II FPGAs 40K->3M gates* *some in pin compatible packages Features: Dual Ported Block Rams Digital Clock Managers DCM Double Data Rate I/O DDR Digitally Controlled Impedance I/O Various I/O signal standards Debugging: Logic Analyser cores FPGAs programmed in VHDL & VERILOG FE-FPGA Cluster Finder TTC TCS Temp Monitor JTAG TCS : Trigger Control System 9U VME64x

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Database Requirements Per FED 25 K strips Per Strip:256 x bits Cluster 2 x 8 bits Enable 1 bits Per APV: 2 x 96 2 bits Per ADC: 1 x 96 8 bits Frame 5 bits 2 bits 8 bits Per OptoRx: 1 x 8 8 bits +... TTCrx settings FPGA configuration FED run settings FED ID Total ~ 100 KBytes +

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Event Readout DAQ Trailer Formatted FED Data DAQ Header Tracker Header? Readout (via VME) Formatted Events identical? to those sent to S-LINK Load Parameters e.g. Peds, Skews Set run mode e.g. Raw Data, TTC clock Start Run and wait for Triggers/Frames Poll on Event Counter Get length of event (Request to) Readout (in chunks) Clear Event & Repeat… Check local status registers/counters i.e. similar to PMC (sorry) Event Formats: Raw Data unprocessed. Scope Mode. Tracker header?

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Software Schedule Work has just started in tandem with Firmware design... These are still guesstimates and depend on the ease of Firmware implementation and the demands of testing… Draft Memory Map internal (end November) Release Event Format specs (end December) Release draft fedlib API spec (basic calls/no code) (end January) Release draft operating instructions (end January) Release first version of fedlib (basic calls/code) (end March) + more needed... DataBase model? Caveat Emptor: It is possible/likely that changes will be necessary to these specs.

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Comments In order to achieve minimum firmware & software on TIB timescales require... Confirmation of functionality needed for TIB tests. Close co-operation between UK and Tracker DAQ group. Arrange small FEDv1 online meeting. Propose contact from UK to visit CERN for “technology transfer”. Keep systems h/w and s/w as close as possible (within UK) and between UK and CERN. Note: We now have additional effort in UK for test software, database, etc. See Testing Talk

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Testing

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Crates Comments 2 FEDv1s to test in UK starting December 2002 FEDv1 is a complex board. Board evaluation will require considerable time and effort Originally aiming for Batch 2 delivery 10? FEDs to CERN Q Testing Design: Hardware Optical/Analogue/Digital & Firmware i.e. Boards aren’t ready one month after receiving them Problems will happen Need for special Test Firmware & Software Common set-ups within UK and with CERN (see Costas’s talk)

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Test Features VME-FPGA TTCrx BE-FPGA Event Builder Buffers FPGA Configuration Power DC-DC DAQ Interface 12 Front-End Modules x 8 Double-sided board CERN Opto- Rx Analogue/Digital 96 Tracker Opto Fibres VME Interface Xilinx Virtex-II FPGA JTAG Boundary Scan: Digital integrity/connections Electrical Analogue Integrity Tests pre OptoRx Xilinx “Chip Scope” Integrated Logic Analyser Cores : Capture raw ADC data (pre VME interface) Opto-Tests with IC Test Board Special FPGA loads e.g. Pattern Generators Additional Test Features: Internal/External Clocks External Triggers FE-FPGA Cluster Finder TTC TCS Temp Monitor JTAG TCS : Trigger Control System 9U VME64x

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Test Plan Draft Test effort in UK shared: RAL Electrical & Digital IC Optical UK test team is sufficient Design vs Production testing Integrity vs Performance testing Hardware vs Firmware* tests Originally foresaw ~ 9 months design testing before Batch 2 *firmware still under development Test Plan Draft

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Testing Schedule Preparation Crates/PSUs/Test Kits/Tools licenses (pre Boards) Pre & Post Assembly tests (~1 week) Basic Power Supply tests (~1 week) Digital Integrity: Boundary Scan JTAG (~1 week) FPGA configuration test JTAG (~1 week) Analogue Integrity*: Signal Gen/Test card + Chip Scope/JTAG (~4 weeks) (Pre VME, board default settings but requires Firmware for Clock set-up in all FPGAs) => Assemble OptoRx Parallel IC Opto Integrity tests at IC : with IC Opto-Test card + Chip Scope (~4 weeks) Basic Digital tests : CFlash FPGA configuration, Clocks TTCrx, QDRs (~6 weeks) (Pre VME, Test card + ChipScope, requires special test Firmware) VME Interface test : PC & VME Link (~4 weeks) (Peek & Poke => Test software) Intermediate Digital Tests (Scope mode, Raw Data mode, Event readout) (~8 weeks) Intermediate Analogue Tests (Pedestals, X-Talk, Step Response) (~6 weeks)

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Testing Schedule 2003 Enough tests done to assemble 2 more FEDv1 for TIB tests VME64x Dynamic addressing, MBLT64 TTCrx advanced Temp sensors DAC offsets Serial ID EPROM In-situ CFlash programming TCS interface S-LINK interface Advanced Analogue: Bandwidth, FFT, Signal/Noise Advanced Digital: High rates and lot more before......Batch 2 go ahead. Design Iteration needed before Batch 2?

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 FEDs for TIB Tests Minimum of 4 months testing from 2003 Jan-April ; Assemble & Test May-June Optimistic scenario TIB FEDs deliver to CERN start July. (exchange second pair with UK FEDv1’s?) Precludes design iteration. Assumes no major test problems. And OptoRx availability. Software API can be provided much earlier.

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting FEDv1 Test Setups & Software Test rig being set up at IC: Crate, PC/Linux + VME Interface Clone system at RAL Analogue Test piggyback card at RAL (1 -> 12 chans) Opto Test VME Card at IC (12 -> 96 chans) Plus TTC systems, FEDKit XDAQ/HAL based fedlib library Dedicated UK Test software also using same fedlib library. Needed in UK in March. Firmware development continuing in parallel. Q. Suitable GUI for test software Qt ? Used LabView in past.

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting CMS Silicon Strip Tracker FED Crate Layout FE 1 DAQ TTC FE 2 FE 3 FE 4 FE 5 FE 6 FE 7 Crate Input Data Rate~ 50 Gbyte/s Crate Output Data Rate~ 1 GByte/s per percent hit occupancy B-Scan F-Bus NN Synch 100 KHz FE 8 Throttle

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting CMS Silicon Strip Tracker FED Counting Room Layout (illustration) 440 Boards96 ADC/Board 24 Crates 8 Racks 440 Boards96 ADC/Board 24 Crates 8 Racks 40 K ADC Channels10 Max Trigger Rate100 kHz Input Rate1.5 T Byte/s Output rate25 Gbyte/s/% 40 K ADC Channels10 Max Trigger Rate100 kHz Input Rate1.5 T Byte/s Output rate25 Gbyte/s/% 4 TTC Partitions DAQ FED

Instrumentation DepartmentJohn Coughlan et al.Rutherford Appleton Laboratory23 October 2002Tracker Electronics Meeting 124 E-Net Switch FEC CRATES DCS Tracker Control WS TTC CRATES DAQ VME SBC RTOS CMS Silicon Strip Tracker FED Control & Monitoring D-BASE R/C 50K ADC Channels FED CRATES