MRF & Cosylab on timing system: integration support Joze Dedic the best people make cosylab … Head of Hardware.

Slides:



Advertisements
Similar presentations
01/11/2002SNS Software Final Design Review1 V123S Event Link Encoder, Transmission System and PLL Receiver Thomas M. Kerner (BNL) SNS Global Controls.
Advertisements

Multi Functional Digital Fault Recorder
Protocol Configuration in Horner OCS
ESS Timing System Plans and Requirements Timo Korhonen Chief Engineer, Integrated Control System Division May 19, 2014.
M. Kreider, T. Fleck WhiteRabbit 1 WhiteRabbit Timing System.
Dirk Zimoch, EPICS Collaboration Meeting, Vancouver 2009 Real-Time Data Transfer using the Timing System (Original slides and driver code by Babak Kalantari)
Dayle Kotturi and Stephanie Allison Facility Advisory Committee Meeting April 20-21,
Extensible Processors. 2 ASIP Gain performance by:  Specialized hardware for the whole application (ASIC). −  Almost no flexibility. −High cost.  Use.
TCSS 372A Computer Architecture. Getting Started Get acquainted (take pictures) Discuss purpose, scope, and expectations of the course Discuss personal.
April 16, 2009 Center for Hybrid and Embedded Software Systems PtidyOS: An Operating System based on the PTIDES Programming.
Target Control Electronics Upgrade 08/01/2009 J. Leaver P. Smith.
Detector Array Controller Based on First Light First Light PICNIC Array Mux PICNIC Array Mux Image of ESO Messenger Front Page M.Meyer June 05 NGC High.
CSS Lecture 2 Chapter 3 – Connecting Computer Components with Buses Bus Structures Synchronous, Asynchronous Typical Bus Signals Two level, Tri-state,
EtherCAT Protocol Implementation Issues on an Embedded Linux Platform
SNS Integrated Control System EPICS Collaboration Meeting SNS Machine Protection System SNS Timing System Coles Sibley xxxx/vlb.
INTRODUCE OF SINAP TIMING SYSTEM
Trigger Supervisor (TS) J. William Gu Data Acquisition Group 1.TS position in the system 2.First prototype TS 3.TS functions 4.TS test status.
RTS Meeting 8th July 2009 Introduction Middleware AUTOSAR Conclusion.
Micro-Research Finland Oy Timing System with Two-Way Signaling cRIO-EVR Jukka Pietarinen EPICS Meeting Padova October 2008.
I/O Example: Disk Drives To access data: — seek: position head over the proper track (8 to 20 ms. avg.) — rotational latency: wait for desired sector (.5.
GBT Interface Card for a Linux Computer Carson Teale 1.
SNS Integrated Control System SNS Timing Master LA-UR Eric Bjorklund.
Lessons Learned The Hard Way: FPGA  PCB Integration Challenges Dave Brady & Bruce Riggins.
Computer Architecture Lecture10: Input/output devices Piotr Bilski.
LCLS Timing Software and Plan 1 Controls Timing Workshop EPICS Collaboration Meeting SLAC LCLS Timing Software and Plan April Kukhee Kim.
IMPROVING THE MRF BASELINE Prague, June 5 th 2014.
Micro-Research Finland Oy Timing System Developments Jukka Pietarinen EPICS Collaboration Meeting Shanghai March 2008.
WP CO Column Status and Progress October 7th, 2010 Johannes Gutleber PR a-JGU, October 7th, 2010 J. Gutleber 1 R. Gutleber.
Henri Kujala Integration of programmable logic into a network front-end of a telecontrol system Supervisor: Professor Patric Östergård Instructor: Jouni.
REDNET Prototype overview Rok Stefanic the best people make cosylab.
ATCA based LLRF system design review DESY Control servers for ATCA based LLRF system Piotr Pucyk - DESY, Warsaw University of Technology Jaroslaw.
Micro-Research Finland Oy Timing System Modules Jukka Pietarinen EPICS Collaboration Meeting, Argonne, June 2006.
Micro-Research Finland Oy MRF Timing System Jukka Pietarinen Timing Workshop CERN February 2008.
Micro-Research Finland Oy Components for Integrating Device Controllers for Fast Orbit Feedback Jukka Pietarinen EPICS Collaboration Meeting Knoxville.
Tool Integration with Data and Computation Grid GWE - “Grid Wizard Enterprise”
CSS 372 Oct 4th - Lecture 3 Chapter 3 – Connecting Computer Components with Buses Bus Structures Synchronous, Asynchronous Typical Bus Signals Two level,
1 Timo Korhonen PSI 1. Concepts revisited…again 3. New (Diamond) cards features and status 4. EPICS interface 5. Conclusions SLS & Diamond Timing System.
Experience Running Embedded EPICS on NI CompactRIO Eric Björklund Dolores Baros Scott Baily.
Hardware proposal for the L2  trigger system detailed description of the architecture mechanical considerations components consideration electro-magnetic.
SNS Integrated Control System Timing Clients at SNS DH Thompson Epics Spring 2003.
Timing Requirements for Spallation Neutron Sources Timing system clock synchronized to the storage ring’s revolution frequency. –LANSCE: MHz.
PR a-JGU, October 9th, 2011 J. Gutleber 1 MedAustron PXI Systems at CERN Johannes Gutleber Roland Moser.
Latest ideas in DAQ development for LHC B. Gorini - CERN 1.
This material exempt per Department of Commerce license exception TSU Xilinx On-Chip Debug.
Connecting EPICS with Easily Reconfigurable I/O Hardware EPICS Collaboration Meeting Fall 2011.
REDNet - Status overview Rok Stefanic Ziga Kroflic
FECOS the best people make cosylab Matej Miha Rok
Fail-Safe Module for Unmanned Autonomous Vehicle
Tool Integration with Data and Computation Grid “Grid Wizard 2”
ProShell Procedure Framework Status MedAustron Control System Week 2 October 7 th, 2010 Roland Moser PR a-RMO, October 7 th, 2010 Roland Moser 1.
XLV INTERNATIONAL WINTER MEETING ON NUCLEAR PHYSICS Tiago Pérez II Physikalisches Institut For the PANDA collaboration FPGA Compute node for the PANDA.
ESS Timing System Prototype 2012 Miha Reščič, ICS
Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 1 Read-out of High Speed S-LINK Data Via a Buffered PCI Card A. Guirao.
BPM stripline acquisition in CLEX Sébastien Vilalte.
CERN Timing Overview CERN timing overview and our future plans with White Rabbit Jean-Claude BAU – CERN – 22 March
Wir schaffen Wissen – heute für morgen Babak Kalantari, PSI MRF workshop, Prague, Eli Beamlines Paul Scherrer Institut Synchronous DAQ using.
CSNS Timing System G. Lei Feb Page CSNS Timing System Feb Contents of this talk Breif introduction to CSNS Requirement investigation Strategy:
Research Unit for Integrated Sensor Systems and Oregano Systems Cern Timing Workshop 2008 Patrick Loschmidt, Georg Gaderer, and Nikolaus Kerö.
Vertical column Joze Dedic … on behalf of CSL MA team the best people make cosylab.
Page Beam Instrumentation mini- workshop Conclusions from the Hardware, Timing and MPS mini-workshop Lund, Miha Reščič Deputy Head of
Software tools for digital LLRF system integration at CERN 04/11/2015 LLRF15, Software tools2 Andy Butterworth Tom Levens, Andrey Pashnin, Anthony Rey.
ESS Timing System Plans Timo Korhonen Chief Engineer, Integrated Control System Division Nov.27, 2014.
Main Timing System Overview
IAPP - FTK workshop – Pisa march, 2013
CALICE DAQ Developments
Beam-Synchronous Data Acquisition (BS-DAQ)
The White Rabbit Fieldbus
LCLS Timing Software and Plan
SLS & Diamond Timing System update
Chapter 13: I/O Systems.
Presentation transcript:

MRF & Cosylab on timing system: integration support Joze Dedic the best people make cosylab … Head of Hardware

Positioning, wrt timing systems Cosylab provides support on the system-integration level …and (unlike MRF) we are not focused on the timing transmission layer  Jukka/MRF remains essential part we understand very well how the EVR and EVG work and we know how to add accelerator specific logic  still hard real-time …but we are also soft  providing drivers or application level SW Cosylab 2010

…to be on the same page about system integration and our role Cosylab 2010

Let’s talk dimensions Cosylab 2010 terminology timing event, transmission rate, clock, time, resolution, jitter, accuracy, time-stamping, response rate, delay propagation compensation… event, data and payload delay compensation strategy PTP (IEEE1588), equal fiber length,... automatic delay compensation data distribution protocol and priorities RT data bus timing domain knowledge huh?

Let’s talk dimensions Cosylab 2010 timing domain knowledge “hardware” dedicated FPGA, must have VHDL timing-receiver code special devices, tightly integrated in timing system SW drivers add IOs for HW triggers (for dummy devices) small add-on to basic FPGA FW code PCB layout; board design is not trivial anymore, and costly VME, PXI… target platform FPGA FW code not complex prototype (Xilinx dev board for <$500) 8b/10b, fiber link FPGA + SFP

Let’s talk dimensions Cosylab 2010 timing domain knowledge “hardware” integration know-how tests, documentation, support, training… (straightforward) implementation slaves; RT part; FPGA,SW part; integrate with “simple” devices, tightly embed with complex devices master; RT part; FPGA, SW part configure hardware (access to the implementation source code, FPGA expert, low-level SW expert…) virtual accelerators, execution slots, deliver user data sync with (patient) breathing, linac grid… sync with mains (but… not too fast for choppers, etc…) machine physics, accelerator/machine specific requirements

Let’s talk dimensions Cosylab 2010 “hardware” timing domain knowledge integration know-how

So… we “live and breath” in the third axis, providing help with system integration.  but for sure, we understand the whole cube Cosylab 2010 “hardware” timing domain knowledge integration know-how

MedAustron MedAustron centre for ion-therapy and research Complete timing system Cosylab 2010

MedAustron timing Cosylab x MRF EVG n-x MRF EVR REDNET = real-time event and data network requirement analysis, architecture design development, testing…  FPGA  LV driver (complete development framework)… MRF network

MA; EVG++ VAcc (ExecSlots), multiple tables; 256 entries, relative delay all tables synced to internal time grid (VAcc specific offset) command / data / XML real time data distro to receiver clients (all per ES) asynchronous events priorities automatic heart beat generation Cosylab 2010

MA; Receiver side digital/optical signals on the MRF EVR outputs distribute events to clients (neighbor PXI cards) trigger clients (neighbor PXI cards) software IRQ (LV Vis) time stamping support distribute reference clock (10 MHz GPS) Cosylab 2010

MA; EVR++ (flex. outputs) Cosylab aux outputs 7 start trigger lines 8 backplane trigger bus PCI IRQ; VIs delay propagation compensation fully flexible output configuration concurrent response generation all events can map to any of the 16 different settings: pulse, delay, width, toggle/pulse (per output, per event) …but still optimized for resource usage

ORNL SNS Spallation neutron source Timing master renovation Cosylab 2010

SNS in the period we cooperated on SNS timing system renovation old HW (several VME crates) moved to single Virtex 5 LX- 50 requirements, architecture, development, testing did not touch transfer layer, only the master Cosylab 2010

SNS; Event Link (EL) Cosylab 2010

SNS; catching mains Cosylab 2010 complete timing operation breathes with mains and waits for choppers (rotation inertia) synthesizing ~60 Hz (50  Hz) to follow mains + PID regulator

and others… We can help you time your machine. Cosylab 2010 And we can save you time.

Our role MRF support with customization FPGA or drivers customizing timing system to the specific machine specially for new machines and upgrades:  requirements gathering  help define conceptual solution  granularity windows, event/payload/data scheme, integrating target devices, concept of virtual accelerators, priorities  take over architectural design; FPGA, drivers… and even complete timing SW support framework  implementation, testing Cosylab 2010

MPS on MRF use MRF for  robust real-time data distro  nodes time sync (post mortem…) we were showing a PCaPAC 2010 Cosylab 2010 generic part; capture inputs, respond locally/globally (data distro) IOs can should be modular logic (in/out relation) should be configurable

Cosylab 2010 …time out.