ELEN654 ATMATM l Signal Integrity Issues » Capacitive Coupling, Resistance, Inductance » Cross talk l Routability design, Coding, and other Design Measures for protection l I/O Design l Packaging Routing Considerations

ELEN654 ATMATM Impact of Interconnect Parasitics Reduce Robustness Affect Performance Increase delay Increase power dissipation Classes of Parasitics Capacitive Resistive Inductive

ELEN654 ATMATM Capacitive Cross Talk

ELEN654 ATMATM Capacitive Cross Talk Dynamic Node 3 x 1  m overlap: 0.19 V disturbance C Y C XY V DD PDN CLK In Y X 2.5 V 0 V

ELEN654 ATMATM Capacitive Cross Talk Driven Node  XY = R Y (C XY +C Y ) Keep time-constant smaller than rise time V (Volt) t (nsec) X Y V X R Y C XY C Y tr↑tr↑

ELEN654 ATMATM Dealing with Capacitive Cross Talk l Avoid floating nodes l Protect sensitive nodes l Make rise and fall times as large as possible l Differential signaling l Do not run wires together for a long distance l Use shielding wires l Use shielding layers

ELEN654 ATMATM Shielding GND Shielding wire Substrate (GND) Shielding layer V DD

ELEN654 ATMATM Cross Talk and Performance CcCc - When neighboring lines switch in opposite direction of victim line, delay increases DELAY DEPENDENT UPON ACTIVITY IN NEIGHBORING WIRES Miller Effect - Both terminals of capacitor are switched in opposite directions (0  V dd, V dd  0) - Effective voltage is doubled and additional charge is needed (from Q=CV)

ELEN654 ATMATM Impact of Cross Talk on Delay r is ratio between capacitance to GND and to neighbor

ELEN654 ATMATM Structured Predictable Interconnect Example: Dense Wire Fabric ([Sunil Kathri]) Trade-off: Cross-coupling capacitance 40x lower, 2% delay variation Increase in area and overall capacitance Also: FPGAs, VPGAs

ELEN654 ATMATM Interconnect Projections Low-k dielectrics l Both delay and power are reduced by dropping interconnect capacitance l Types of low-k materials include: inorganic (SiO 2 ), organic (Polyimides) and aerogels (ultra low-k) l The numbers below are on the conservative side of the NRTS roadmap 

ELEN654 ATMATM Encoding Data Avoids Worst- Case Conditions Encoder Decoder Bus In Out

ELEN654 ATMATM Information Theoretic Approach to Address Delay and Reliability in Long On-chip Interconnects Interconnects

ELEN654 ATMATM Overview

ELEN654 ATMATM Sources of Error on Interconnects l Capacitive Coupling l Inductive Coupling l Process Variations l Power Noise

ELEN654 ATMATM Signal Integrity l Tradition: »Protect the signal on every single wire. »Design the clock period to be greater than the worst case delay. l Questions asked? »Is it an overkill? »Can some errors be tolerated? »Can this be optimized?

ELEN654 ATMATM Capacitive Coupling l Signals are influenced by the signals in the adjacent wires due to coupling capacitance l Phenomenon known as “Crosstalk” l Results in “Deterministic” Delay Variations

ELEN654 ATMATM Modeling Interconnects I(s) G(s) O(s) l O(s) = G(s).I(s)

ELEN654 ATMATM Modeling Interconnects I(s) G(s)O(s) Capacitive Coupling Structure

ELEN654 ATMATM Modeling Interconnects I(s) G(s)O(s) Inductive Coupling Structure

ELEN654 ATMATM Modeling Interconnects I(s) G(s)O(s) Power Noise Randomness

ELEN654 ATMATM Modeling Interconnects I(s) G(s)O(s) Process Variations Randomness

ELEN654 ATMATM Transfer Function l O(s) = F(s).I(s) l F(s) = (1 + L(s)C(s)) - 1

ELEN654 ATMATM Bus Delay

ELEN654 ATMATM Bus Delay

ELEN654 ATMATM Waveform s

ELEN654 ATMATM

ATMATM Problems in Interconnects l Delay l Power l Reliability

ELEN654 ATMATM Binary Symmetric Channel l Inputs, Outputs Є {0,1} l Crossover Probability p e 0 1 pepe 1-p e 1 0 pepe

ELEN654 ATMATM Self Information (of an event) l Defined as »- log 2 (p) –p is the probability of occurrence. l Example »if 1 occurs with p = ½, then every time it occurs -log2(1/2) = 1 bits of information is conveyed.

ELEN654 ATMATM Entropy l Entropy of a system of random events is the measure of uncertainty l Defined as » H(S)= -Σ p.log 2 (p) –p is the probability of occurrence of each event in the system. l Example: »For a random binary system –H = - p 1.log 2 (p 1 ) - p 0.log 2 (p 0 ) –If p 1 = p 0 = ½, H = 1 bit.

ELEN654 ATMATM Conditional Entropy l The uncertainty in one system, given the outcome of the second system. l Defined as »H(S 1 |S 2 ) = -Σ Σ p jk.log 2 (p jk /p k ) –J and k are events in systems 1 and 2 respectively. –The equation represents the entropy of system1 conditioned upon the outcome of system 2.

ELEN654 ATMATM Channel Capacity l reduction in uncertainty about the input given the output l C = H(S i ) – H(S i |S o ) l For p 1 = p 0 = ½ »C = 1 + p e.log 2 (p e ) + (1-p e ).log 2 (1-p e )

ELEN654 ATMATM Channels with memory l Have multiple states »A 1, A 2,…, A n l Each state has a probability of occurrence »p 1,p 2,…,p n l Each state has a probability of error »p e1,p e2,…,p en l Capacity of each state »C i = 1 + p ei log(p ei ) + (1+p ei ) log(1+p ei ) l Capacity of channel »C=Σ p i C i

ELEN654 ATMATM The States

ELEN654 ATMATM Capacity

ELEN654 ATMATM Capacity

ELEN654 ATMATM

ATMATM

ATMATM l Concluding Remark »Non of the simple ad-hoc codes are approaching the capacity l Current/Future work »Capacity-approaching bus codes.. and bus design

ELEN654 ATMATM Driving Large Capacitances V in V out C L V DD Transistor Sizing Cascaded Buffers

ELEN654 ATMATM Using Cascaded Buffers C L = 20 pF InOut 12N 0.25  m process Cin = 2.5 fF tp 0 = 30 ps F = CL/Cin = 8000 fopt = 3.6 N = 7 tp = 0.76 ns

ELEN654 ATMATM Output Driver Design Trade off Performance for Area and Energy Given t pmax find N and f l Area l Energy

ELEN654 ATMATM Delay as a Function of F and N Number of buffer stages N , t p / t p 0 F = F = 1000 F = 10,000 t p /t p0

ELEN654 ATMATM Output Driver Design Transistor Sizes for optimally-sized cascaded buffer t p = 0.76 ns Transistor Sizes of redesigned cascaded buffer t p = 1.8 ns 0.25  m process, C L = 20 pF

ELEN654 ATMATM How to Design Large Transistors G(ate) S(ource) D(rain) Multiple Contacts small transistors in parallel Reduces diffusion capacitance Reduces gate resistance

ELEN654 ATMATM Bonding Pad Design Bonding Pad Out In V DD GND 100  m GND Out

ELEN654 ATMATM ESD Protection l When a chip is connected to a board, there is unknown (potentially large) static voltage difference l Equalizing potentials requires (large) charge flow through the pads l Diodes sink this charge into the substrate – need guard rings to pick it up.

ELEN654 ATMATM ESD Protection Diode

ELEN654 ATMATM Chip Packaging Bond wires (~25  m) are used to connect the package to the chip Pads are arranged in a frame around the chip Pads are relatively large (~100  m in 0.25  m technology), with large pitch (100  m) Many chips areas are ‘pad limited’

ELEN654 ATMATM Pad Frame LayoutDie Photo

ELEN654 ATMATM Chip Packaging l An alternative is ‘flip-chip’: »Pads are distributed around the chip »The soldering balls are placed on pads »The chip is ‘flipped’ onto the package »Can have many more pads

ELEN654 ATMATM Tristate Buffers In En V DD Out Out = In.En + Z.En V DD In En Out Increased output drive

ELEN654 ATMATM Reducing the swing  Reducing the swing potentially yields linear reduction in delay  Also results in reduction in power dissipation  Delay penalty is paid by the receiver  Requires use of “sense amplifier” to restore signal level  Frequently designed differentially (e.g. LVDS)

ELEN654 ATMATM Single-Ended Static Driver and Receiver

ELEN654 ATMATM Dynamic Reduced Swing Network f In 2. f 1. f M 2 M 1 M 3 M 4 C bus C out BusOut V DD V V(Volt) f V bus V asym V sym 246 time (ns)

ELEN654 ATMATM Impact of Resistance l We have already learned how to drive RC interconnect l Impact of resistance is commonly seen in power supply distribution: »IR drop »Voltage variations l Power supply is distributed to minimize the IR drop and the change in current due to switching of gates

ELEN654 ATMATM RI Introduced Noise M 1 X I R 9 R D V f pre D V V DD V 2D V 9 I

ELEN654 ATMATM

ATMATM Resistance and the Power Distribution Problem Source: Cadence Requires fast and accurate peak current prediction Requires fast and accurate peak current prediction Heavily influenced by packaging technology Heavily influenced by packaging technology Before After

ELEN654 ATMATM Power Distribution l Low-level distribution is in Metal 1 l Power has to be ‘strapped’ in higher layers of metal. l The spacing is set by IR drop, electromigration, inductive effects l Always use multiple contacts on straps

ELEN654 ATMATM Power and Ground Distribution

ELEN654 ATMATM 3 Metal Layer Approach (EV4) 3rd “coarse and thick” metal layer added to the technology for EV4 design Power supplied from two sides of the die via 3rd metal layer 2nd metal layer used to form power grid 90% of 3rd metal layer used for power/clock routing Metal 3 Metal 2 Metal 1 Courtesy Compaq

ELEN654 ATMATM 4 Metal Layers Approach (EV5) 4th “coarse and thick” metal layer added to the technology for EV5 design Power supplied from four sides of the die Grid strapping done all in coarse metal 90% of 3rd and 4th metals used for power/clock routing Metal 3 Metal 2 Metal 1 Metal 4 Courtesy Compaq

ELEN654 ATMATM 2 reference plane metal layers added to the technology for EV6 design Solid planes dedicated to Vdd/Vss Significantly lowers resistance of grid Lowers on-chip inductance 6 Metal Layer Approach – EV6 Metal 4 Metal 2 Metal 1 RP2/Vdd RP1/Vss Metal 3 Courtesy Compaq

ELEN654 ATMATM Electromigration (1)

ELEN654 ATMATM Electromigration (2)

ELEN654 ATMATM Resistivity and Performance Diffused signal propagation Delay ~ L 2 C N-1 CNCN C2C2 R1R1 R2R2 C1C1 TrTr V in R N-1 R N The distributed rc-line

ELEN654 ATMATM The Global Wire Problem Challenges l No further improvements to be expected after the introduction of Copper (superconducting, optical?) l Design solutions »Use of fat wires »Insert repeaters — but might become prohibitive (power, area) »Efficient chip floorplanning l Towards “communication-based” design »How to deal with latency? »Is synchronicity an absolute necessity?  outwwd dwwd CRCRCRCRT 

ELEN654 ATMATM Interconnect Projections: Copper Copper is planned in full sub-0.25  m process flows and large-scale designs (IBM, Motorola, IEDM97) With cladding and other effects, Cu ~ 2.2  -cm vs. 3.5 for Al(Cu)  40% reduction in resistance l Electromigration improvement; 100X longer lifetime (IBM, IEDM97) »Electromigration is a limiting factor beyond 0.18  m if Al is used (HP, IEDM95) Vias

ELEN654 ATMATM Interconnect: # of Wiring Layers # of metal layers is steadily increasing due to: Increasing die size and device count: we need more wires and longer wires to connect everything Rising need for a hierarchical wiring network; local wires with high density and global wires with low RC 0.25  m wiring stack

ELEN654 ATMATM Diagonal Wiring y x destination Manhattan source diagonal 20+% Interconnect length reduction Clock speed Signal integrity Power integrity 15+% Smaller chips plus 30+% via reduction Courtesy Cadence X-initiative

ELEN654 ATMATM Using Bypasses Driver Polysilicon word line Metal word line Metal bypass Driving a word line from both sides Using a metal bypass WL Kcells

ELEN654 ATMATM Reducing RC-delay Repeater

ELEN654 ATMATM Repeater Insertion (Revisited) Taking the repeater loading into account For a given technology and a given interconnect layer, there exists an optimal length of the wire segments between repeaters. The delay of these wire segments is independent of the routing layer!

ELEN654 ATMATM Inductance Issues L di/dt Impact of inductance on supply voltages: Change in current induces a change in voltage Longer supply lines have larger L C L V’ DD V L i(t) V out V in GND’ L

ELEN654 ATMATM L di/dt: Simulation Input rise/fall time: 50 psecInput rise/fall time: 800 psec decoupled Without inductors With inductors

ELEN654 ATMATM Dealing with Ldi/dt l Separate power pins for I/O pads and chip core. l Multiple power and ground pins. l Careful selection of the positions of the power and ground pins on the package. l Increase the rise and fall times of the off-chip signals to the maximum extent allowable. l Schedule current-consuming transitions. l Use advanced packaging technologies. l Add decoupling capacitances on the board. l Add decoupling capacitances on the chip.

ELEN654 ATMATM Choosing the Right Pin

ELEN654 ATMATM Decoupling Capacitors Decoupling capacitors are added: on the board (right under the supply pins) on the chip (under the supply straps, near large buffers)

ELEN654 ATMATM De-coupling Capacitor Ratios l EV4 »total effective switching capacitance = 12.5nF »128nF of de-coupling capacitance »de-coupling/switching capacitance ~ 10x l EV5 »13.9nF of switching capacitance »160nF of de-coupling capacitance l EV6 »34nF of effective switching capacitance »320nF of de-coupling capacitance -- not enough! Source: B. Herrick (Compaq)

ELEN654 ATMATM EV6 De-coupling Capacitance Design for  Idd= 25 Vdd = 2.2 V, f = 600 MHz »0.32-µF of on-chip de-coupling capacitance was added –Under major busses and around major gridded clock drivers –Occupies 15-20% of die area »1-µF 2-cm 2 Wirebond Attached Chip Capacitor (WACC) significantly increases “Near-Chip” de- coupling –160 Vdd/Vss bondwire pairs on the WACC minimize inductance Source: B. Herrick (Compaq)

ELEN654 ATMATM EV6 WACC Source: B. Herrick (Compaq)

ELEN654 ATMATM The Transmission Line The Wave Equation

ELEN654 ATMATM Design Rules of Thumb l Transmission line effects should be considered when the rise or fall time of the input signal (t r, t f ) is smaller than the time-of-flight of the transmission line (t flight ). t r (t f ) << 2.5 t flight Transmission line effects should only be considered when the total resistance of the wire is limited: R < 5 Z 0 The transmission line is considered lossless when the total resistance is substantially smaller than the characteristic impedance, R < Z 0 /2

ELEN654 ATMATM Should we be worried? l Transmission line effects cause overshooting and non- monotonic behavior Clock signals in 400 MHz IBM Microprocessor (measured using e-beam prober) [Restle98]

ELEN654 ATMATM Matched Termination Z 0 Z L Z 0 Series Source Termination Z 0 Z 0 Z S Parallel Destination Termination

ELEN654 ATMATM Segmented Matched Line Driver

ELEN654 ATMATM Parallel Termination─ Transistors as Resistors 0.5 Normalized Resistance ( V ) 1 PMOS with-1V bias NMOS-PMOS PMOS only NMOS only 1.5 V R (Volt) Out M r V dd Out M r V dd V bb Out M rp M rn V dd

ELEN654 ATMATM Output Driver with Varying Terminations V out (V) V out (V) 1234 time (sec) Revised design with matched driver impedance V s V d V in Initial design V s V d V in

ELEN654 ATMATM The “Network-on-a-Chip” Embedded Processors Memory Sub-system Memory Sub-system Accelators Configurable Accelerators Peripherals Interconnect Backplane