WRM FUTURE DEVELOPMENT DANIELE FELICI (ER1), ALI ABDALLAH (ESR1) WP2 EDUSAFE MEETING CERN, JUNE 2015.

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Presentation transcript:

WRM FUTURE DEVELOPMENT DANIELE FELICI (ER1), ALI ABDALLAH (ESR1) WP2 EDUSAFE MEETING CERN, JUNE 2015

SUMMARY Introduction Hardware development plans Today status Future plans

AFTER THE TESTING CAMPAIGN After the testing campaign a full-software solution is ready Each block of the scheme has been tested (performances and speed) Edge detectors: Canny algorithm Vs Zero Crossing algorithm WRM simulation: different parameters have been tuned in order to increase the performances. The parameters are fundamental for the development of the hardware under development Line Segment reconstructor: the algorithm has been optimized The entire “WRM system” has been compared with Hough and LSD methods for segments detection. The results are very promising What about hardware?

WHAT ABOUT HARDWARE FPGA (under development) ASIC (already developed in the past) FPGA or Software

FPGA Due to the short period an FPGA solution is preferred to an ASIC solution Fast delivery time Development steps can be used for ASIC development High versatility, essential for the system optimization Xilinx VC 707 evaluation board, based on Virtex 7: High performances High connectivity Affordable costs

ARCHITECTURE PROPOSAL (1) WRM ImagesEdges 8-pixel segments 8-pixel segments or long segments (TBD) Through Ad-hoc interface Through Ethernet, PCIe, USB… (needs evaluation)

ARCHITECTURE PROPOSAL (2) WRM Images (paralinx) Edges 8-pixel segments 8-pixel segments or long segments (TBD) Through Ethernet, PCIe, USB… (needs evaluation) Through Ad-hoc interface Images pass- trough (HDMI)

ARCHITECTURE PROPOSAL (3) WRM Images (second paralinx) Edges 8-pixel segments 8-pixel segments or long segments (TBD) Through Ethernet, PCIe, USB… (needs evaluation) Through Ad-hoc interface Images (paralinx)

TODAY STATUS FPGA is in our hands Edge detector implementation on FPGA is ongoing We are adapting the algorithm for the HW implementation

FUTURE PLANS Finish edge detector implementation FPGA-WRM interface needs to be developed Server-FPGA interface needs to be developed Line segments reconstructions Test and validation (Testing Campaign)

THANK YOU