Welcome to the ECE 449 Computer Design Lab Spring 2005

ECE 449: Computer Design Lab Course Coordinator: Kris Gaj Course Instructors, TAs: Monday section: Milind M. Parelkar Tuesday section: Milind M. Parelkar Thursday section: Kamal Sayeed

ECE 449: Computer Design Lab Change in lab hours Canceled Section 203: Class time: Tuesday, 4:30-7:10 PM Created Section 204: Class time: Thursday, 7:20-10:00 PM

ECE 449 Section Preference Form First Name:Kevin Last Name:Smith

Please clearly mark your preferences on the distributed form Your assignment to a particular lab section will be determined by Friday, January 28, and sent to you by You do NOT need to do anything to move to the right section or move your name from the waiting list to the registered status All assignments are FINAL and cannot be changed in the middle of the semester Section Assignment Rules (1)

You are welcome to attend any of the three office hour sessions Please attend the class meetings of the other section only in case of emergency and give preference in access to the lab computers to the students attending the right section All experiment demonstrations and report submissions need to be done in the presence of your TA, and can be done exclusively during the class time of your section Section Assignment Rules (2)

ECE 449: Computer Design Lab Course Coordinator – Primary Responsibilities: Course Instructors, TAs – Primary Responsibilities: - Introductory lectures and hands-on sessions - Teaching how to use software, hardware and testing equipment needed for experiments - Holding office hours - Grading student demonstrations and reports - Help in preparation of introductory lectures and new experiments - Coordination of work done by the TAs - Enforcing consistent policies and grading standards - Mid-semester student satisfaction survey - Resolving conflicts and providing feedback to TAs

Lab Access Rules and Behavior Code Please refer to the FPGA Design & Test Lab website:

ECE 331 ECE 332 ECE 280  C ECE 445  C ECE 442 ECE 447  C ECE 449 Digital Systems & Computers PHYS 261PHYS 262 or

Tasks of the course Advanced course on digital system design with VHDL Comprehensive introduction to FPGA technology Testing equipment - writing VHDL code for synthesis - RTL VHDL - finite state machines - test benches - hardware: Xilinx FPGAs - software: VHDL simulator Synthesis tools Xilinx ISE - oscilloscope - logic analyzer

VHDL for Specification VHDL for Simulation VHDL for Synthesis

Levels of design description Algorithmic level Register Transfer Level Logic (gate) level Circuit (transistor) level Physical (layout) level Level of description most suitable for synthesis

Register Transfer Logic (RTL) Design Description Combinational Logic Combinational Logic Registers …

VHDL Design Styles Components and interconnects structural VHDL Design Styles dataflow Concurrent statements behavioral Registers State machines Test benches Sequential statements Subset most suitable for synthesis

Testbenches Testbench Environment TB Processes Generating Stimuli Design Under Test (DUT) Stimuli All DUT Inputs Simulated Outputs

FPGAs vs. ASICs ASICs FPGAs High performance Off-the-shelf Short time to the market Low development costs Reconfigurability Low power Low cost (but only in high volumes)

Design process (1) Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds….. Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; ); end AES_core; Specification (Lab Experiments) VHDL description (Your Source Files) Functional simulation Post-synthesis simulation Synthesis

Design process (2) Implementation Configuration Timing simulation On chip testing

Simulation Tools

Synthesis Tools

architecture MLU_DATAFLOW of MLU is signal A1:STD_LOGIC; signal B1:STD_LOGIC; signal Y1:STD_LOGIC; signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC; begin A1<=A when (NEG_A='0') else not A; B1<=B when (NEG_B='0') else not B; Y<=Y1 when (NEG_Y='0') else not Y1; MUX_0<=A1 and B1; MUX_1<=A1 or B1; MUX_2<=A1 xor B1; MUX_3<=A1 xnor B1; with (L1 & L0) select Y1<=MUX_0 when "00", MUX_1 when "01", MUX_2 when "10", MUX_3 when others; end MLU_DATAFLOW; VHDL description Circuit netlist Logic Synthesis

Implementation After synthesis the entire implementation process is performed by FPGA vendor tools

Design Process control from Active-HDL

XESS Inc. Educational Boards

FPGA available on the board Xilinx Spartan 2, XC2S ,000 equivalent logic gates 1200 CLB slices Up to 200 MHz clock Programmable Interconnects Configurable Logic Block slices (CLB slices) Block RAMs 10 4-kbit block RAMs

Digital system design technologies Microprocessors ASICs FPGAs ECE 445 ECE 442 ECE 447 ECE 586 ECE 680 ECE 681 ECE 449 ECE 511 ECE 611 ECE 431 Computer Organization Digital Computer Design & Interfacing Single Chip Microcomputers Computer Design Lab Digital Circuit Design Microprocessors Advanced Microprocessors VLSI Design Automation Computer Arithmetic Digital Integrated Circuits Physical VLSI Design ECE 545 Introduction to VHDL ECE 645 ECE 545, 645, 681

Prerequisites: ECE 445 VHDL: - writing synthesizable RTL level code in VHDL - writing test benches FPGAs: - architecture of FPGA devices - tools for the computer-aided design with FPGAs - current FPGA families & future trends Topics covered: STARTING IN SPRING 2006: NEW COURSE ECE 448, FPGA and ASIC Design with VHDL

Applications: Platforms: - basics of computer arithmetic - applications from communications, coding theory, and cryptography - FPGA boards - microprocessor board – FPGA board interfaces: PCI, PCI-X High-level ASIC Design: - standard cell implementation approach - logic synthesis tools - differences between FPGA & standard-cell ASIC design flow

Integration with ECE 449 into one 4 credit hour course ECE credit hour VHDL intro + FPGA intro + hands-on tools intro + experiment intro + lab time 4 credit hours Lecture Lab NEW COURSE, ECE 448 VHDL intro + FPGA intro + ASIC intro + more advanced lectures on applications and platforms hands-on tools intro + experiment intro + lab time Lab

Why ECE 449 is a challenging course? no associated lecture need to “relearn” VHDL need to learn tools need to perform practical experiments time needed to complete experiments only one credit hour

What can not be changed this semester? too much work for 1 credit hour Re: Organization think positive - you pay for one credit hour, you are getting three credit hours of instruction - even if you get a bad grade (>= D) it will not ruin your GPA your curriculum is a package - there are easy courses worth 3 credit hour

Student self-evaluation: Spring – worse than expected 6 – as well as expected 1 – better than expected

Difficulties: Spring 2004 finding time to do the lab - 6 too many other classes taken in the same semester - 6 understanding - 4 getting used to tools - 3 midterm - 2

Why is this course worth taking? VHDL for synthesis: one-of-the-most-sought-after skills knowledge of state-of-the-art tools used in the industry knowledge of the modern FPGA technology knowledge of state-of-the-art testing equipment design portfolio that can be used during job interviews unique knowledge and practical skills that make you competitive at the job market