Designing of a D Flip-Flop Final Project ECE 491.

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Presentation transcript:

Designing of a D Flip-Flop Final Project ECE 491

Objectives To familiarize with the function of the D flip- flop and it's operation. To Draw the schematic and the layout with clocked input Perform DRC check and generate LVS To do the simulation and observed the output waveforms To Vary the output load(1pf to 5pf) and observed outputs

D Flip Flop (Specification) A signal input and a clock signal is used AMI-0.6micron process is used Wp=7.5 u, Wn= 3.0 u, Ln=Lp=0.6u Pre and Post-layout simulations using spectra Rise time, Fall time and propagation delay increase for the loading effects

Why DFF Preferred type for integrated circuit applications (DFF) S-R flip flop has indeterminate state when both inputs are high The JKFF simplifies the RSFF truth table but keeps two inputs.

Symbol CLK D Q QB DFF

Layout

Inverter And NorAnd Nor Q QB Schematics

AND NOR NAND INVERTER

Results

Delay

Without load

Loading Effect

Negative Edged Trigger

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