A non-volatile Flip-Flop in Magnetic FPGA chip W.Zhao, E. Belhaire, V. Javerliac, C. Chappert, B. Dieny Design and Test of Integrated Systems in Nanoscale.

Slides:

Advertisements

Similar presentations

Ultra Low Power RF Section of a Passive Microwave RFID Transponder in 0.35 μm BiCMOS Giuseppe De Vita, Giuseppe Iannaccone Dipartimento di Ingegneria dell’Informazione:

Advertisements

Differential pass transistor pulsed latch Moo-Young Kim, Inhwa Jung, Young-Ho Kwak, Chulwoo Kim 指導老師 : 魏凱城老師學生 : 蕭荃泰彰化師範大學積體電路設計研究所.

Design and Application of Power Optimized High-Speed CMOS Frequency Dividers.

1 A New Successive Approximation Architecture for Low-Power Low-Cost A/D Converter IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.38, NO.1, JANUARY 2003 Chi-sheng.

Spartan II Features  Plentiful logic and memory resources –15K to 200K system gates (up to 5,292 logic cells) –Up to 57 Kb block RAM storage  Flexible.

Montek Singh COMP Sep 8,  Previous class: ◦ Basics of magnetism ◦ Nanomagnets and their coupling  TODAY: ◦ Challenges and Benefits  reliability.

Pinched Hysteresis Loops of Two Memristor SPICE Models Akzharkyn Izbassarova and Daulet Kengesbek Department of Electrical and Electronics Engineering.

Magnetic sensors and logic gates Ling Zhou EE698A.

M -RAM (Magnetoresistive – Random Access Memory) Kraków, 7 XII 2004r.

A Wideband Low Power VCO for IEEE a

M2: Team Paradigm :: Milestone 7 2-D Discrete Cosine Transform Group M2: Tommy Taylor Brandon Hsiung Changshi Xiao Bongkwan Kim Project Manager: Yaping.

Rail-to-rail low-power high-slew-rate CMOS analogue buffer

A Dynamic GHz-Band Switching Technique for RF CMOS VCO

A 0.35μm CMOS Comparator Circuit For High-Speed ADC Applications Samad Sheikhaei, Shahriar Mirabbasi, and Andre Ivanov Department of Electrical and Computer.

1 A 0.6V ULTRA LOW VOLTAGE OPERATIONAL AMPLIFIER 指導教授：林志明所長指導學生：賴信吉：彰師大積體電路設計研究所.

12/1/2004EE 42 fall 2004 lecture 381 Lecture #38: Memory (2) Last lecture: –Memory Architecture –Static Ram This lecture –Dynamic Ram –E 2 memory.

A filter free class D audio amplifier with 86% power efficiency Muggler, P., Chen, W., Jones, C., Dagli, P., Yazdi, N., ISCAS '04. Proceedings of the 2004.

1 CMOS Temperature Sensor with Ring Oscillator for Mobile DRAM Self-refresh Control IEEE International Symposium on Circuits and Systems, Chan-Kyung.

1 姓名 : 李國彰指導教授 : 林志明老師 A 1v 2.4GHz CMOS POWER AMPLIFIER WITH INTEGRATED DIODE LINEARIZER ( The 2004 IEEE Asia-Pacific Conference on Circuits and Systems,

1 A 56 – 65 GHz Injection-Locked Frequency Tripler With Quadrature Outputs in 90-nm CMOS Chan, W.L.; Long, J.R.; Solid-State Circuits, IEEE Journal of.

Design of a GHz Low-Voltage, Low-Power CMOS Low-Noise Amplifier for Ultra-wideband Receivers Microwave Conference Proceedings, APMC 2005.

1 SERIAL PORT INTERFACE FOR MICROCONTROLLER EMBEDDED INTO INTEGRATED POWER METER Mr. Borisav Jovanović, Prof.dr Predrag Petković, Prof.dr. Milunka Damnjanović,

A 12-bit, 300 MS CMOS DAC for high-speed system applications

Magnetoresistive Random Access Memory (MRAM)

學生 : 蕭耕然馮楷倫蘇承道指導教授 : 李泰成老師

Guohe Yin, U-Fat Chio, He-Gong Wei, Sai-Weng Sin,

Semiconductor Memories.  Semiconductor memory is an electronic data storage device, often used as computer memory, implemented on a semiconductor-based.

1 Power Amplifier With Low Average Current and Compact Output Matching Network 指導老師 : 林志明學生 : 黃政德系級 : 積體所研一 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS,

Design of a 10 Bit TSMC 0.25μm CMOS Digital to Analog Converter Proceedings of the Sixth International Symposium on Quality Electronic Design IEEE, 2005.

A 1 Volt CMOS Pseudo Differential Amplifier Apirak Suadet and Varakorn Kasemsuwan Department of Electronics, Faculty of Engineering, King Mongkut's Institute.

指導教授：林志明老師研究生：林高慶學號：s

A Single Capacitor Bootstrapped Power Efficient CMOS Driver José C. García, Juan A. Montiel–Nelson Institute for Applied Microelectronics, Department of.

系所:積體電路設計研究所指導教授:林志明學生:鄭士豪

1 A Frequency Synthesizer Using Two Different Delay Feedbacks 班級：積體所碩一學生：林欣緯指導教授：林志明教授 Circuits and Systems, ISCAS IEEE International Symposium.

1 Successive Approximation Analog-to- Digital Conversion at Video Rates 指導教授：汪輝明學生：陳柏宏.

Ultra-low-Power Smart Temperature Sensor with Subthreshold CMOS Circuits International Symposium on Intelligent Signal Processing and Communications, 2006.

Design of Low-Power Analog Drivers Based on Slew-Rate Enhancement Circuits for CMOS Low-Dropout Regulators IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II:

1 Bus Encoding for Total Power Reduction Using a Leakage-Aware Buffer Configuration 班級：積體所碩一學生：林欣緯指導教授：魏凱城老師 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION.

A Low-Voltage CMOS Rail-to-Rail Operational Amplifier Using Double P-Channel Differential Input Pairs 指導教授：林志明老師研究生：賴信吉 MAIL ：

Comparative Analysis of Ultra-Low Voltage Flip-Flops for Energy Efficiency Bo Fu and Paul Ampadu IEEE International Symposium on Circuits and Systems,pp ,

New Power Saving Design Method for CMOS Flash ADC Institute of Computer, Communication and Control, Circuits and Systems, July 2004 IEEE 班級：積體碩一姓名：黃順和.

A Linearized Cascode CMOS Power Amplifier 指導教授：林志明老師研究生：林高慶學號： Ko, Sangwon; Lin, Jenshan; Wireless and Microwave Technology Conference, 2006.

A HIGH-SPEED LOW-POWER RAIL-TO-RAIL BUFFER AMPLIFIER FOR LCD APPLICATION C-W Lu; Xiao, P.H.; Electrical and Computer Engineering, Canadian Conference on.

Magnetic Random Access Memory Jonathan Rennie, Darren Smith.

02/21/2003 CART 1 On-chip MRAM as a High-Bandwidth, Low-Latency Replacement for DRAM Physical Memories Rajagopalan Desikan, Charles R. Lefurgy, Stephen.

SPINTRONICS …… A QUANTUM LEAP PRESENTED BY: DEEPAK 126/05.

Charge Recycling in MTCMOS Circuits: Concept and Analysis

1 A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC 班級 : 積體所碩一學生 : 林義傑 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER 2003.

學生 : 李國彰指導教授 : 賴永齡老師 A 1.5V 2.4GHz CMOS Mixer with high linearity ( The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, December 6-9, 2004.

An Analysis of THD in Class D Amplifiers

A 2.4-GHz 0.18-um CMOS Self-Biased Cascode Power Amplifier

Chapter 5: CAPACITANCE and INDUCTANCE

Introduction to Spintronics

LARC 研究群 – 晶片驗證實驗室 LARC – VLSI Verification Lab. 指導老師：清華大學電機系黃錫瑜副教授辦公室 : 資電館 818 室 Circuit Model test patterns = expected.

指導老師 : 王瑞騰老師學生 : 盧俊傑 On Cognitive Radio Networks with Opportunistic Power Control Strategies in Fading Channels IEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS,

Overview of VLSI 魏凱城彰化師範大學資工系. VLSI  Very-Large-Scale Integration Today’s complex VLSI chips  The number of transistors has exceeded 120 million 

Click to edit Master title style Progress Update Energy-Performance Characterization of CMOS/MTJ Hybrid Circuits Fengbo Ren 05/28/2010.

Submitted To: Presented By : Dr R S Meena Shailendra Kumar Singh Mr Pankaj Shukla C.R. No : 07/126 Final B. Tech. (ECE) University College Of Engineering,

Analysis to Peak-to-Average Power Ratio in OFDM Systems 指導老師 : 黃文傑博士研究生 : 吳濟廷

Introduction to Field Programmable Gate Arrays (FPGAs) EDL Spring 2016 Johns Hopkins University Electrical and Computer Engineering March 2, 2016.

SPINTRONICS Submitted by: K Chinmay Kumar N/09/

This project has received funding from the European Union’s Horizon 2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement.

Magnetoresistive Random Access Memory (MRAM)

指導老師：王明賢老師學生：黃品翰日期：2015/1/15

A CMOS Operational Amplifier with Constant 68° phase margin over its whole range of noise-power trade-off programmability Meier auf der Heide, P.; Bronskowski,

Overview of VLSI 魏凱城彰化師範大學資工系.

STT-MRAM Tapeouts: IBM 65nm & IBM 45nm SOI

Modeling and Design of STT-MRAMs

Literature Review A Nondestructive Self-Reference Scheme for Spin-Transfer Torque Random Access Memory (STT-RAM) —— Yiran Chen, et al. Fengbo Ren 09/03/2010.

Presentation transcript:

A non-volatile Flip-Flop in Magnetic FPGA chip W.Zhao, E. Belhaire, V. Javerliac, C. Chappert, B. Dieny Design and Test of Integrated Systems in Nanoscale Technology, pp , 2006 指導老師 : 魏凱城老師學生 : 蕭荃泰日期 : 97 年 4 月 14 日彰化師範大學積體電路設計研究所

Outline  Abstract  Magnetic Flip-Flop  Magnetic Standard Non-Volatile Flip-Flop  MSFlip-Flop Simulation  Conclusion

Abstract  The propose a non-volatile flip-flop, which presents simultaneously low power dissipation and high speed.  This flip-flop is based on MRAM (Magnetic RAM) technology on standard CMOS.  In this non-volatile flip-flop design, we use Magnetic Tunnel Junctions (MTJ) as storage element.  In this paper, a magnetic flip-flop is proposed to make the FPGA circuit completely non-volatile.

Magnetic Flip-Flop Fig1. the position of MTJs  Magnetic tunnel junction (MTJ) structure consisting of two ferromagnetic metals separated by a thin insulating layer.

Fig3. Magnetic Flip-Flop structuresFig2. SRAM based Master-Slave Flip-Flop structure

Fig4. schema of SRAM based sense amplifier

Fig5. Magnetic writing circuits

The simulation of magnetic Flip-Flop

Fig6. (a) Magnetic Standard mixed Flip-Flop schema (b) Magnetic Standard mixed Flip-Flop symbol (a) (b) Magnetic Standard Non-Volatile Flip-Flop

MSFlip-Flop Simulation  In the magnetic-standard flip-flop simulation, the low frequency control signal “ NW ” is 10 KHz, the clock frequency is 500MHz and the input frequency is 250MHz.  130nm technologies have been used for the CMOS part, and a complete simulation model has been developed by CEA for the magnetic part.

Fig7. The simulation results of magnetic standard non-volatile Flip-Flop. The last Data saved in MTJ is ‘ 1 ’

Fig8. The simulation results of magnetic standard non-volatile Flip-Flop. The last Data saved in MTJ is ‘ 0 ’

The flip-flop keeps the non-volatility of 1/X times (X is the ratio of processing frequency and the low, user defined frequency)

Conclusion  We proposed this new architecture of Magnetic Standard flip-flop which features simultaneously non-volatility, high speed and low power dissipation.  This flip-flop can also be used to replace all the registers in SOC (System-on-chip) then makes these chips non-volatile and secure.

The end