ECO Timing Optimization Using Spare Cells Yen-Pin Chen, Jia-Wei Fang, and Yao-Wen Chang ICCAD2007, Pages ICCAD2007, Pages

Outline Introduction Introduction Problem Formulation Problem Formulation The Spare-Cell Selection Algorithm The Spare-Cell Selection Algorithm Experimental Results Experimental Results Conclusions Conclusions

Outline Introduction Introduction Problem Formulation Problem Formulation The Spare-Cell Selection Algorithm The Spare-Cell Selection Algorithm Experimental Results Experimental Results Conclusions Conclusions

Introduction Spare cells are often used to perform ECO (Engineering Change Order) after the placement stage to change/fix a design. They are often evenly placed on the chip layout; the type and number of spare cells vary from different chip designs and are usually determined by designers empirically.

Introduction Using spare cells is an efficient way to do netlist changes. Using spare cells is an efficient way to do netlist changes. Save time and effort of re-placing the netlist Save time and effort of re-placing the netlist Save production cost of masks Save production cost of masks

Outline Introduction Introduction Problem Formulation Problem Formulation The Spare-Cell Selection Algorithm The Spare-Cell Selection Algorithm Experimental Results Experimental Results Conclusions Conclusions

Problem Formulation A timing path is defined as A timing path is defined as (1) A path from a primary input to a primary output (2) A path from a primary input to a flip-flop input (3) A path from a flip-flop output to a primary output (4) A path between a flip-flop output and a flip-flop input An ECO path is a timing path that violates the timing constraint. An ECO path is a timing path that violates the timing constraint.

Problem Formulation A buffering operation is to insert a buffer-type spare cell g S (i) into a net n E (j) along an ECO path. A buffering operation is to insert a buffer-type spare cell g S (i) into a net n E (j) along an ECO path. A gate sizing operation is to exchange a spare cell g S (i) with a gate g E (j) along an ECO path by rewiring. A gate sizing operation is to exchange a spare cell g S (i) with a gate g E (j) along an ECO path by rewiring.

Outline Introduction Introduction Problem Formulation Problem Formulation The Spare-Cell Selection Algorithm The Spare-Cell Selection Algorithm Experimental Results Experimental Results Conclusions Conclusions

Timing Model and Properties Synopsys Liberty library format Synopsys Liberty library format Use lookup table to calculate gate delays. Use lookup table to calculate gate delays. The gate delay and the output transition time are functions of the output loading and the input transition time. The gate delay and the output transition time are functions of the output loading and the input transition time.

Timing Model and Properties Loading dominance Loading dominance The effect of its output capacitance to the gate delay is much larger than that of the input transition time.(28x vs 1x) The effect of its output capacitance to the gate delay is much larger than that of the input transition time.(28x vs 1x) Shielding effect Shielding effect Change of the netlist effects delay of neighbor gates only. Change of the netlist effects delay of neighbor gates only.

Algorithm Overview

Buffer Insertion We keep the solution if d’(g E (M−1))+d’(g S (j)) < d(g E (M−1)), M: size of G E

Gate Sizing

Spare-Cell Selection inside a Bounding Polygon Let the width of the square bounding box of g E (i) centered at g E (i) be Let the width of the square bounding box of g(j) (g(j) ∈ G(j)) centered at g(j) be : the capacitance per unit wirelength C EO (i) : the output pin capacitance of gate g E (i). FO(g E (i)) : the set of fan-out gates of g E (i) G(j) : the fan-outs of the gate g E (i) to be sized

Spare-Cell Selection inside a Bounding Polygon

Let the width of the square bounding box of g(k) (g(k) ∈ G(k)) centered at g(k) be Let the width of the square bounding box of g(j) (g(j) ∈ G(j)) centered at g(j) be G(k) : the fan-ins of the gate g E (i) to be sized G(j) : the fan-outs of the gate g E (i) to be sized

Solution Control For each set of solutions, we keep at most k solutions. (k is a user-defined parameter) For each set of solutions, we keep at most k solutions. (k is a user-defined parameter) Discard non-dominant solutions. Discard non-dominant solutions. Classify these solutions by the number of used buffers. Classify these solutions by the number of used buffers. Keep the best K solutions for each class. Keep the best K solutions for each class.

Outline Introduction Introduction Problem Formulation Problem Formulation The Spare-Cell Selection Algorithm The Spare-Cell Selection Algorithm Experimental Results Experimental Results Conclusions Conclusions

Shielding Effect

ECO Timing Optimization

Outline Introduction Introduction Problem Formulation Problem Formulation The Spare-Cell Selection Algorithm The Spare-Cell Selection Algorithm Experimental Results Experimental Results Conclusions Conclusions

Conclusions This paper present the first work for this problem of ECO timing optimization using spare-cell rewiring. They didn’t solve the competition for using a spare cell among multiple paths. They can’t insert multiple buffers in a single net.

Thanks

Timing Model and Properties Output loading consists of Output loading consists of input pin capacitance input pin capacitance output pin capacitance output pin capacitance wire loading wire loading c : is the capacitance per unit wirelength, F O (g(i)) : the set of fan-out gates of g(i) C O (i) : output pin capacitance of gate g(i) C I (j) : input pin capacitance of the fan-outs of the gate g(i)

Gate Sizing and Buffer Insertion Buffering on the net n E (i) changes the delay of the driving gate and driven gates of n E (i), while other gates are little or not affected. Thus the impact of buffering on the timing of the ECO path is the delay change of g E (i), g E (i + 1), and the delay increase of the inserted buffer. Sizing the gate g E (i) changes the delay of the fan-in/fan- out gates of g E (i), while other gates are little or not affected. Thus the impact of sizing g E (i) on the timing of the ECO path is the delay change of g E (i − 1), g E (i + 1), and the sized gate.

Gate Sizing We keep the solution if d’(g E (M −2))+d’(g S (j)) < d(g E (M − 2))+d(g E (M −1)),and d’(g E (M −2)) < d(g E (M −2)),

Spare-Cell Selection inside a Bounding Polygon Theorem 1: Given a net n E (i) with the source g E (i) and the sinks in G(j) to be buffered, inserting any buffer-type spare cell, whose output transition time is not smaller than g E (i) and with the same output loading, outside the bounding polygon Γ(i) into the net increases the path delay.