Presenter : Ching-Hua Huang 2012/6/25 A High-Throughput, Metastability-Free GALS Channel Based on Pausible Clock Method Mohammad Ali Rahimian, Siamak Mohammadi, Mohammad Fattah Dependable Systems Design Lab, School of ECE, University of Tehran, Tehran, Iran nd Asia Symposium on Quality Electronic Design (ASQED) National Sun Yat-sen University Embedded System Laboratory

Synchronization issues such as metastability in multi-clock domain systems have become a big problem, reducing data transmission throughput between domains. In this paper, a high-throughput, metastability-free data transmission channel based on pausible clock method in Globally-Asynchronous Locally-Synchronous (GALS) systems is proposed. This channel can be used as the interconnection of mixed-clock synchronous IP cores without having concerns about their synchronization. We show that the probability of metastability in our design is practically zero; and this without loss of throughput and latency, allowing the transmitter and receiver to operate with their own maximum clock frequency. The proposed channel is simulated in 90nm CMOS process using Predictive Technology Model (PTM) library. Gate delays and power parameters are extracted from Spice simulations and are back annotated into our channel HDL code. The throughput, latency and power are analyzed and compared with existing designs. 2 PTM is developed by the Nanoscale Integration and Modeling (NIMO) Group at ASU.

3 Related work [This paper] A High-Throughput, Metastability-Free GALS Channel Based on Pausible Clock Method FIFO The main component of the proposed channel [3] GALS design Asynchronous Pausible clock Loosely synchronous [2] GALS systems are introduced in 80's [4]~[8] comparison [22]~[26] [1] Modules Reusability and communication between them in GALS [9]~[21] Recent research : high-throughput, low-latency, ANoC Some approaches of GALS design early

4 What’s the problem  Metastability is a serious problem in multi- clock domain system ◦ It will reduce data transmission throughput  If a storage into Metastability, its value of output will shock between 0 and 1  The cause for occurrence of Metastability ◦ I will explain at next page  Common solve approaches of Metastability ◦ 2 Flip-Flop ◦ FIFO

5 tsu is the setup time th is the hold time tmet is the metastable state that possible to continue If the clock of storage close to rising edge. The storage maybe into Metastability. When a data input from one clock to another clock of storage

6 2 Flip-Flop Synchronizer can’t eliminate Metastability completely, but it can reduce the probability of occurrence. 2 Flip-Flop Synchronizer 1.The probability of occurrence of Metastability ∝ Clock rate 2.If we implement this circuit at 500MHz frequency, the average time between two Metastability occurs is 1.9x10 22 years. (Refer from senior Chi-Guang)

7 0x00 0x04 … 0xFF Read pointer Write pointer Full/Empty happen Handle different clock

8 Proposed method : A High-Throughput, Metastability-Free GALS Channel Assume FIFO depth = three

9 Transmitter : 1. TxReady (Ready transmit signal) 2. TxData (Data bus) 3. IF the FIFO full, TxRun will be ternon to pause the TxClk Receiver: The same with transmitter.

10 (1)FIFO depth = three. (2)The receiver is faster that transmitter. TxData TxReady TxRun TxClk RxData RxReady RxRun RxClk put talk headAddr tailAddr full empty

11 (After three consecutive write operations) (After two write and a read operations) There is no possibility for the metastability to occur. The only possible situation to have the metastability is when the FIFO is empty, the transmitter sends a new data, the receiver's clock is resumed and the written data is read.

12 The internal architecture of FIFO Two adders are needed to increment the head and tail registers

13Result: compared with other design The comparison between the throughput of this paper design and that of [22] is shown in Figure. Comparison of Latency, Throughput and Power Consumption with Word Length = 64

A pausible based GALS interconnect and its FIFO are proposed and their detail descriptions are discussed. The proposed channel is implemented in Verilog with back-annotated standard cells. This paper’s design is better in throughput, latency, and power consumption while its area overhead is more than previous works. 14

15 This paper help me to realize more information about GALS and its detailed descriptions. The design of senior Chi-Guang is using 2 Flip-flop and FIFO to implement the IP-OCP interface. A perfect design is not existing We should to sacrifice a little factor to improve other factor