BI-TB on BST Systems Introduction (L. Jensen) Hardware for SPS/LHC masters and receivers (old and new) (JJ. Savioz) Software for masters and receivers.

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Presentation transcript:

BI-TB on BST Systems Introduction (L. Jensen) Hardware for SPS/LHC masters and receivers (old and new) (JJ. Savioz) Software for masters and receivers (L. Jensen) BST systems used for LHC experiments (S. Baron/L. Jensen) RF signal distribution for SPS and LHC (W. Hofle) Consolidation ideas for the BST systems (J. Serrano) Beam synchronous signals for PS (H. Damerau) Conclusions and outlook (All) Lars K. Jensen1

Introduction Transmission of ‘hardware’ signals (Frev, 40MHz, pre-pulses) + message (LHC: 64 bytes / turn) Hardware consists of: – 3 central masters: SPS LHC Beam 1 LHC Beam 2 – BOBR receivers (+new VFC-based modules) Main use (BI): – Acquisition clocks and triggering + time- stamping of BI systems (“DAB64x”) through the BOBR receiver BPM, BLM, BRAN, BSRA, BSRT, BCTF.. LHC: presently have >130 BOBR devices Objectives for the meeting today: – Inform of what’s available today – Agree on responsibilities (present and future) – Discuss consolidation plans (SPS/LHC) – Details concerning PS BST (Heiko) Lars K. Jensen2

Master Message LHC Message: – _wiki/LHC/BST-config _wiki/LHC/BST-config EDMS document (2008): – Lars K. Jensen3

BI acquisition triggers (defined and used for BPM/BLM) Allow triggering all distributed systems within n*100ps for timing events on 1msec frame Lars K. Jensen4

Master software BST Master project started as collaboration in 2004 – P. Karlsson (BI), D. Dominguez (CO), J. Lewis (CO) VME hardware clone of “MTG” module -> “BST- CTG” (FPGA micro-controller) – Tasks with software written in assembler- language, compiled before download Global (GR) and per task registers (R) FESA (2.10) class and BST tasks developed and maintained by BI/SW – PPC4 OS - port to L865 will likely await 2014 Regular orbit-trigger every “GR11” msec Initialisation – wait for 1 PPS event Orbit on bit #2 of byte 9 Count-down Lars K. Jensen5

BOBR software BDI_BOBR hardware-type in CCDB Device driver for PPC4 and L865 based on ‘dgII’ Handling of two hardware-bytes sent on the BI-only Wiener-crates (P0 lines rows D/E) VME interrupts based on setup of message byte and bit masks FESA 2.10 class developed and maintained by BI/SW (ported to L865) Lars K. Jensen6