Module 1.2 Verilog Simulator.  A Verilog program for a particular application consists of two blocks : ◦ Design Block (Module) ◦ Testing Block (Stimulus.

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Presentation transcript:

Module 1.2 Verilog Simulator

 A Verilog program for a particular application consists of two blocks : ◦ Design Block (Module) ◦ Testing Block (Stimulus )

Design Methodologies: Two types of design methodologies  Top Down Design  Bottom Up Design Design Block inputs outputs

 In Top Down design methodology, we define the top level block and identify the sub-blocks necessary to build the top level block. We further divide the sub-block until we come to the leaf cells, which are the cells which cannot be divided.

 In a Bottom Up design methodology, we first identify the building blocks, we build bigger blocks using these building blocks. These cells are then used for high level block until we build the top level block in the design

 The basic lexical conventions used by Verilog HDL are similar to those in the C programming language.  Verilog HDL is a case-sensitive language.  All keywords are in lowercase.

 White space characters are : ◦ Blank spaces ◦ Tabs ◦ Carriage returns ◦ New-line.  These characters are ignored except when they serve to separate other tokens.  However, blanks and tabs are significant in strings.

There are two forms to introduce comments. Examples of Comments  Single line comments begin with the token // and end with a carriage return  Multi Line comments begin with the token  /* and end with the token */

 Verilog HDL is case sensitive ◦ Lower case letters are unique from upper case letters ◦ All Verilog keywords are lower case  Examples of Unique names : input // a Verilog Keyword wire // a Verilog Keyword WIRE // a unique name ( not a keyword) Wire // a unique name (not a keyword) NOTE : Never use the Verilog keywords as unique name, even if the case is different.

 Identifiers are names used to give an object, such as a register or a module, a name so that it can be referenced from other places in a description. ◦ Identifiers must begin with an alphabetic character or the underscore character ( a-z; A-Z _ ) ◦ Identifiers may contain alphabetic characters, numeric characters, the underscore, and the dollar sign ( a-z ; A-Z ; 0-9 ; _ $ ) ◦ Identifiers can be up to 1024 characters long.

 Examples of legal identifiers data_input clk_input my$clk i386 A  Escaped Identifiers : Verilog HDL allows any character to be used in an identifier by escaping the identifier. Escaped identifiers provide a means of including any of the printable ASCII characters in an identifier.  Examples of escape identifiers: \486_up \Q~ \1,2,3 \reset*

 You can specify constant numbers in decimal, hexadecimal, octal, or binary format.  Negative numbers are represented in 2's complement form.  When used in a number, the question mark (?) character is the Verilog alternative for the z character.