"A probabilistic approach to clock cycle prediction" A probabilistic approach to clock cycle prediction J. Dambre, D. Stroobandt and J. Van Campenhout TAU, December 2, 2002

"A probabilistic approach to clock cycle prediction" Outline System-level interconnect predictionSystem-level interconnect prediction Prediction of minimal clock cyclePrediction of minimal clock cycle New probabilistic approachNew probabilistic approach Experimental resultsExperimental results Main causes of errorsMain causes of errors Conclusions & future workConclusions & future work

"A probabilistic approach to clock cycle prediction" System-level interconnect prediction Predict length distribution of interconnections in final implementation Predict length distribution of interconnections in final implementation Measured or typical values Parameters from interconnect topology Technology and design parameters Real or hypothetical

"A probabilistic approach to clock cycle prediction" System-level interconnect prediction Parameters from interconnect topology Technology and design parameters Wire length distribution Probabilistic: wire length variability across multiple layout runswire length variability across multiple layout runs assumed homogeneous: all point-to- point wires “drawn” independently from same distributionassumed homogeneous: all point-to- point wires “drawn” independently from same distribution Not : accurate lengths of individual wires for particular run!

"A probabilistic approach to clock cycle prediction" System-level interconnect prediction Parameters from interconnect topology Technology and design parameters Wire length distribution Interconnect lengths affect: routing requirements (cost!)routing requirements (cost!) power dissipationpower dissipation yieldyield performance (clock cycle)performance (clock cycle) etc....etc....

"A probabilistic approach to clock cycle prediction" System-level interconnect prediction Parameters from interconnect topology Technology and design parameters Wire length distribution Assess/compare impact of, e.g.: new/future technological parametersnew/future technological parameters physical design options (e.g. layout or cell aspect ratio)physical design options (e.g. layout or cell aspect ratio) optimization algorithms that change circuit topologyoptimization algorithms that change circuit topology without having to perform physical design!

"A probabilistic approach to clock cycle prediction" Outline System-level interconnect predictionSystem-level interconnect prediction Prediction of minimal clock cyclePrediction of minimal clock cycle New probabilistic approachNew probabilistic approach Experimental resultsExperimental results Main causes of errorsMain causes of errors Conclusions & future workConclusions & future work

"A probabilistic approach to clock cycle prediction" Prediction of minimal clock cycle Distribution of gate and wire delays Distribution and expected value of minimal clock cycle Parameters from interconnect topology Technology and design parameters Wire length distribution

"A probabilistic approach to clock cycle prediction" Previous work: prediction of critical path delay in BACPAC (1) Distribution of gate and wire delays Distribution and expected value of minimal clock cycle Wire length distribution Length of average and global wire Delays of average and global “gate+wire” Critical path delay addition (max. logic depth) (1) Sylvester et al., SLIP 1999

"A probabilistic approach to clock cycle prediction" (2) Iqbal et al., SLIP 2002 Previous work: prediction of critical path delay distribution (2) Distribution of “gate+wire” delays Distribution and expected value of minimal clock cycle Wire length distribution Distribution and expected value of critical path delay Monte Carlo sampling (max. logic depth) Concept: average delay  delay of average wire

"A probabilistic approach to clock cycle prediction" Prediction of minimal clock cycle? Problem: minimal clock cycle relates to maximal combinatorial delay ! Maximal logic depth does not model : equal logic depth, but different number of pathsequal logic depth, but different number of paths paths with less than maximal logic depth can also become slowestpaths with less than maximal logic depth can also become slowest Need model that captures impact of parallellism on extreme value !! => more important as interconnect represents ever increasing fraction of total delay !

"A probabilistic approach to clock cycle prediction" Outline System-level interconnect predictionSystem-level interconnect prediction Prediction of minimal clock cyclePrediction of minimal clock cycle New probabilistic approachNew probabilistic approach Experimental resultsExperimental results Main causes of errorsMain causes of errors Conclusions & future workConclusions & future work

"A probabilistic approach to clock cycle prediction" Prediction of minimal clock cycle? Parameters from interconnect topology Technology and design parameters Distribution of gate and wire delays Available: “gate+wire” (= segment) delay distribution“gate+wire” (= segment) delay distribution topology of circuit graphtopology of circuit graphAssumption: homogeneous: all individual segment delays “drawn” independently from same distributionhomogeneous: all individual segment delays “drawn” independently from same distribution Distribution and expected value of minimal clock cycle ?

"A probabilistic approach to clock cycle prediction" Prediction of minimal clock cycle: probabilistic principles Sum of independent variables? log(P(d)) log(d) log(P(D)) log(d) log(P(d)) log(d) ? log(P(D)) log(d) ? log(P(D)) log(d) ? convolution of distributions (discrete or continuous)

"A probabilistic approach to clock cycle prediction" Sum of independent variables: path delay distribution as a function of logic depth depth 1 depth 10 depth 8 depth 6 depth 4 depth 2

"A probabilistic approach to clock cycle prediction" Prediction of minimal clock cycle: probabilistic principles use cumulative distributions log(P(d)) log(d) log(P(D)) log(d) log(P(D)) log(d) ? log(P(d)) log(d) log(P(d)) log(d) Maximum of independent variables?

"A probabilistic approach to clock cycle prediction" Maximum of independent variables: maximum path delay distribution for independent paths (logic depth = 4) 1 path 10 paths 8 paths 6 paths 4 paths 2 paths

"A probabilistic approach to clock cycle prediction" Prediction of minimal clock cycle: independent paths? Segment delays might be approximately independent, but paths in a circuit are generally not independent! Find interconnect topology with: same number of wire segmentssame number of wire segments independent paths onlyindependent paths only approx. same clock cycle distributionapprox. same clock cycle distribution Basic concept of new approach: uncoupling of dependencies!

"A probabilistic approach to clock cycle prediction"CriticalitySegments CriticalitySegments CriticalitySegments CriticalitySegments depth 6 depth 5depth 4 depth 3 Prediction of minimal clock cycle: independent paths? Definition: wire criticality = maximal depth of any path through that wire

"A probabilistic approach to clock cycle prediction" Prediction of minimal clock cycle: independent paths? Notion: Sensitivity of clock cycle to individual wire delay strongest on paths with depth = wire criticality Approximations: 1.Ignore impact on clock cycle through paths with smaller depth 2.Assume that wires with equal criticality have equal impact on clock cycle

"A probabilistic approach to clock cycle prediction" Prediction of minimal clock cycle: independent path model Equivalent topology: find wire criticalities (possible without enumeration of all paths !)find wire criticalities (possible without enumeration of all paths !) for each depth i: equivalent paths(i) = nets(crit = i) / ifor each depth i: equivalent paths(i) = nets(crit = i) / iCriticalitySegments Eq. paths

"A probabilistic approach to clock cycle prediction" Outline System-level interconnect predictionSystem-level interconnect prediction Prediction of minimal clock cyclePrediction of minimal clock cycle New probabilistic approachNew probabilistic approach Experimental resultsExperimental results Main causes of errorsMain causes of errors Conclusions & future workConclusions & future work

"A probabilistic approach to clock cycle prediction" Prediction of minimal clock cycle Parameters from interconnect topology Technology and design parameters Distribution of segment delays Distribution and expected value of minimal clock cycle

"A probabilistic approach to clock cycle prediction" Technology parameters from ITRS (ed. 2001, technology node 2001)Technology parameters from ITRS (ed. 2001, technology node 2001) Delay models from BACPAC (e.g. Sakurai, Chern,...)Delay models from BACPAC (e.g. Sakurai, Chern,...) Segment delays Experimental validation 68 benchmarks from LGSynth series: sizes of 527 to blockssizes of 527 to blocks logic depths of 6 to 284logic depths of 6 to 284 Measured distribution of maximal path delays 100 placement runs each Predicted distribution of maximal path delays segment criticality distribution segment delay distribution max. path delay Benchmark circuits 1.traditional: sum of average segment delays 2.new

"A probabilistic approach to clock cycle prediction" Experimental validation Correlation: (traditional) (new)

"A probabilistic approach to clock cycle prediction" Experimental validation Average relative error: -29.3% (traditional) 6.7% (new) Within 10%: 10/68 (14.7%)10/68 (14.7%) 38/68 (55.9%)38/68 (55.9%) Within 20%: 21/68 (30.9%)21/68 (30.9%) 53/68 (77.9%)53/68 (77.9%)

"A probabilistic approach to clock cycle prediction" Outline System-level interconnect predictionSystem-level interconnect prediction Prediction of minimal clock cyclePrediction of minimal clock cycle New probabilistic approachNew probabilistic approach Experimental resultsExperimental results Main causes of errorsMain causes of errors Conclusions & future workConclusions & future work

"A probabilistic approach to clock cycle prediction" Validity of assumptions? They ignore that: some wires may almost always be long/short (locally different distribution)some wires may almost always be long/short (locally different distribution) there might be local correlations between wire lengths (not independent)there might be local correlations between wire lengths (not independent) Both prediction strategies assume that individual wire lengths are independent and equally distributed random variables

"A probabilistic approach to clock cycle prediction" Validity of assumptions? Monte Carlo experiment to meet assumptions: take measured segment delay distributiontake measured segment delay distribution randomly assign delay from distribution to all segments and find maximal path delayrandomly assign delay from distribution to all segments and find maximal path delay repeat 1000 times for each circuitrepeat 1000 times for each circuit Only cause of remaining errors can be equivalent topology! Are deviations due to these assumptions or to equivalent topology?

"A probabilistic approach to clock cycle prediction" Assumptions or equivalent topology? Correlation: (traditional, vs ) (new, vs )

"A probabilistic approach to clock cycle prediction" Average relative error: % (vs. –29.3 %) -7.1 % (vs. 6.7 %) Assumptions or equivalent topology? Within 20%: 7.4% (vs. 30.9%)7.4% (vs. 30.9%) 98.5% (vs. 77.3%)98.5% (vs. 77.3%) Within 10%: 2.9% (vs. 14.7%)2.9% (vs. 14.7%) 63.2% (vs. 55.9%)63.2% (vs. 55.9%)

"A probabilistic approach to clock cycle prediction" Remaining errors? Our equivalent path topology fully uncouples all paths. Rather systematical underestimation of approximately 7% But there are alternatives: with same number of segments,with same number of segments, also using criticalities,also using criticalities, for which distributions can be calculated !for which distributions can be calculated !

"A probabilistic approach to clock cycle prediction" Remaining errors? Example: measured average clock cycle using segment delay distr. from one of the benchmark experimentsmeasured average clock cycle using segment delay distr. from one of the benchmark experiments result: clock cycle (a) 7.1 % below clock cycle (b)result: clock cycle (a) 7.1 % below clock cycle (b) (a) (b) Total uncoupling of paths seems too strong! Can model be tuned to include this effect?

"A probabilistic approach to clock cycle prediction" Outline System-level interconnect predictionSystem-level interconnect prediction Prediction of minimal clock cyclePrediction of minimal clock cycle New probabilistic approachNew probabilistic approach Experimental resultsExperimental results Main causes of errorsMain causes of errors Conclusions & future workConclusions & future work

"A probabilistic approach to clock cycle prediction" Conclusions New probabilistic model for clock cycle prediction:New probabilistic model for clock cycle prediction: captures the essence of circuit parallellismcaptures the essence of circuit parallellism based on equivalent graph topology with independent paths based on equivalent graph topology with independent paths Significantly improved accuracy reached within same assumptions as existing workSignificantly improved accuracy reached within same assumptions as existing work Experimentally verified that most of the remaining errors are due to these assumptionsExperimentally verified that most of the remaining errors are due to these assumptions They are OK for many circuits, but very bad for some!They are OK for many circuits, but very bad for some!

"A probabilistic approach to clock cycle prediction" Future work More experiments to validate model sensitivity to design options its and usefulness for different applicationsMore experiments to validate model sensitivity to design options its and usefulness for different applications Combine model with predicted wire length distributionsCombine model with predicted wire length distributions Try to find mathematical foundations for equivalent topologyTry to find mathematical foundations for equivalent topology Try to incorporate local effects and study some alternative topologiesTry to incorporate local effects and study some alternative topologies

"A probabilistic approach to clock cycle prediction" Prediction of minimal clock cycle: independent path model Non-integer number of paths ? Paths of equal depth have identical delay distribution: No problem: use non-integer values of m !

"A probabilistic approach to clock cycle prediction" ‘mm30a’: an example... Clearly shows inhomogeneity, with many of the most critical segments systematically having low delays Benchmark mm30a Criticality Average wire length