Characterization Presentation Spring 2010 ASIC Tester Abo-Raya Dia- 4 th year student Damouny Samer- 4 th year student 10-April1 Supervised by: Ina Rivkin

10-April2 Overview : Objective: testing the ASIC’s functional correctness Comparing the provider’s input with the expected outputs Providing options for viewing and analyzing the results

10-April3 PC ASIC tester ASIC tester Project Description : FPGA NOGA StarII DUT Adaptive board User Interface GiDEL PROCe PCIe

So Far 10-April4

5 Technical specifications : The tester supports up to 96 inputs/outputs and up to 48 bi-directional pins. Samples I/O signals up to 100 MHz rate. Independent voltage suppliers: -10 v- 10v. 1G memory for each input and output vectors. Two clk pins.

10-April6 Hardware : Sending the vectors from DDR A to FIFO IN (working with the high Freq. ) Transferring the vectors to the DUT via the voltage translators on the PSDB (working with the DUT Freq. ) Sampling the DUT outputs and saving them in DDR B

10-April7 Software : Configuring the ports Defining the ASIC’s work conditions (clocks & voltage level ) Sending the input vectors to the DDR Comparing the outputs with the expected outputs. Configuration mode screenDebug mode screen

10-April8 New Features

10-April9 1.The Loop command : Send the vectors between lines a & b N times. Requirements: a.Loop nesting : 2. b.Writing the output vectors to the output file in a cyclic way. c.The need to match between the inputs & outputs. Hardware Changes :

10-April10 2. Embedded Logic Analyzer : Allow the user to see the signals between the FPGA & the DUT, when a trigger occured. Requirements : a. In order to see the signals, the User should launch Altera Signal Tap, with no need to compile the design. b. To raise the trigger when we recognize a combination of the input Data.

10-April11 3. Waves Library: Creating an input vectors based on waves library, e.g. : counter (increment/decrement), pulse, random, const. value,compound clk (clk edges time,frequency, Duty cycle ). Counter : start from a, each clock cycle increment or decrement the vector by x, till you reach b. Software Changes :

10-April12 4. Sampling frequency: Allow the user to sample the outputs with a higher frequency than the DUT. 5. Graph : A graph for all the output files, when each file was with another frequency.

10-April13 Summary: The new debug mode Logic Analyzer Loop Load wave Sampling Freq. Summary Graph

10-April14 Gant chart :