Kris Gaj Office hours: Monday, 7:30-8:30 PM, Tuesday & Thursday 4:30-5:30 PM, and by appointment Research and teaching interests: cryptography computer arithmetic VLSI design and testing Contact: Engineering Bldg., room 3225 (703)

ECE 645 Part of: MS in EE MS in CpE Digital Systems Design – pre-approved course Other concentration areas – elective course Certificate in VLSI Design/Manufacturing PhD in IT PhD in ECE

DIGITAL SYSTEMS DESIGN 1. ECE 545 Digital System Design with VHDL – K. Gaj, project, FPGA design with VHDL, Aldec/Xilinx/Altera 2. ECE 645 Computer Arithmetic – K. Gaj, project, FPGA design with VHDL or Verilog, Aldec/Xilinx/Altera/Synopsys 3. ECE 586 Digital Integrated Circuits – D. Ioannou 4. ECE 681 VLSI Design for ASICs – N. Klimavicz, project/lab, front-end and back-end ASIC design with Synopsys tools 5. ECE 682 VLSI Test Concepts – T. Storey, homework

Prerequisites Permission of the instructor, granted assuming that you know VHDL or Verilog,High level programming language (preferably C) ECE 545 Digital System Design with VHDL or

Prerequisite knowledge This class assumes proficiency with the FPGA CAD tools from ECE 545 You are expected to be proficient with: –Synthesizable VHDL coding –Advanced VHDL testbenches, including file input/output –Xilinx FPGA synthesis and post-synthesis simulation –Xilinx FPGA place-and-route and post-place and route simulation –Reading and interpreting all synthesis and implementation reports

Course web page ECE web page  Courses  Course web pages  ECE 645

Computer Arithmetic LectureProject Project 1 20 % Project 2 30 % Homework 10 % Midterm exam (in class) 15 % Final Exam (in class) 25 %

Advanced digital circuit design course covering addition and subtraction multiplication division and modular reduction exponentiation Efficient Integers unsigned and signed Real numbers fixed point single and double precision floating point Elements of the Galois field GF(2 n ) polynomial base

1. Applications of computer arithmetic algorithms. Initial Discussion of Project Topics. INTRODUCTION Lecture topics

1. Basic addition, subtraction, and counting 2. Carry-lookahead, carry-select, and hybrid adders 3. Adders based on Parallel Prefix Networks ADDITION AND SUBTRACTION

MULTIOPERAND ADDITION 1. Carry-save adders 2. Wallace and Dadda Trees 3. Adding multiple unsigned and signed numbers

TECHNOLOGY 1. Internal Structure of Xilinx and Altera FPGAs 2. Two-operand and multi-operand addition in FPGAs 3. Pipelining

Unsigned Integers Signed Integers Fixed-point real numbers Floating-point real numbers Elements of the Galois Field GF(2 n ) NUMBER REPRESENTATIONS

LONG INTEGER ARITHMETIC 1.Modular Exponentiation 2.Montgomery Multipliers and Exponentiation Units

MULTIPLICATION 1. Tree and array multipliers 2. Sequential multipliers 3. Multiplication of signed numbers and squaring

TECHNOLOGY Multiplication in Xilinx and Altera FPGAs - using distributed logic - using embedded multipliers - using DSP blocks

DIVISION 1.Basic restoring and non-restoring sequential dividers 2. SRT and high-radix dividers 3. Array dividers

FLOATING POINT AND GALOIS FIELD ARITHMETIC 1.Floating-point units 2. Galois Field GF(2 n ) units

Literature (1) Required textbook: Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design, 2 nd edition, Oxford University Press, 2010.

Literature (2) Jean-Pierre Deschamps, Gery Jean Antoine Bioul, Gustavo D. Sutter, Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems, Wiley-Interscience, Milos D. Ercegovac and Tomas Lang Digital Arithmetic, Morgan Kaufmann Publishers, Isreal Koren, Computer Arithmetic Algorithms, 2nd edition, A. K. Peters, Natick, MA, Recommended textbooks:

Literature (2) 1.Pong P. Chu, RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability, Wiley-IEEE Press, Volnei A. Pedroni, Circuit Design with VHDL, The MIT Press, Sundar Rajan, Essential VHDL: RTL Synthesis Done Right, S & G Publishing, VHDL books:

Literature (3) Supplementary books: 1.E. E. Swartzlander, Jr., Computer Arithmetic, vols. I and II, IEEE Computer Society Press, Alfred J. Menezes, Paul C. van Oorschot, and Scott A. Vanstone, Handbook of Applied Cryptology, Chapter 14, Efficient Implementation, CRC Press, Inc., 1998.

Literature (3) Proceedings of conferences ARITH - International Symposium on Computer Arithmetic ASIL - Asilomar Conference on Signals, Systems, and Computers ICCD - International Conference on Computer Design CHES - Workshop on Cryptographic Hardware and Embedded Systems Journals and periodicals IEEE Transactions on Computers, in particular special issues on computer arithmetic. IEEE Transactions on Circuits and Systems IEEE Transactions on Very Large Scale Integration IEE Proceedings: Computer and Digital Techniques Journal of VLSI Signal Processing

Homework reading assignments design of small hardware units using VHDL analysis of computer arithmetic algorithms and implementations

Midterm exams Midterm Exam - 2 hrs 30 minutes, in class multiple choice + short problems Final Exam – 2 hrs 45 minutes comprehensive conceptual questions, analysis and design of arithmetic units Practice exams on the web Midterm Exam - Monday, March 28 Final Exam - Tuesday, May 16, 4:30-7:15 PM Tentative days of exams:

Project 1 Project I (individual, 20% of grade) Optimizing addition in Skein Final report due Monday, March 14 Choosing optimal architecture for combinational adder pipelined adder in Xilinx FPGAs (Virtex 5 & Virtex 6) Altera FPGAs (Stratix III & Stratix IV) ASICs (bonus) Done individually

27 Basic Operations of 14 SHA-3 Candidates 27 NTT – Number Theoretic Transform, GF MUL – Galois Field multiplication, MUL – integer multiplication, mADDn – multioperand addition with n operands

28 Basic operation in Skein x1 and Skein x4 Basic operation, MIX, in Skein x1 (basic iterative) Basic operation, MIX, in Skein x4 (4 times unrolled)

29 How to Increase the Speed? : The case for pipelining and parallel processing Protocols: IPSec, SSL, WLAN (802.11) Required Throughput Range: 100 Mbit/s - 40 Gbit/s (based on the specs of Security Processors from Cavium Networks, HiFn, and Broadcom) Supported sizes of packets: 40B B 1500 B = Maximum Transmission Unit (MTU) for Ethernet v2 576 B = Maximum Transmission Unit (MTU) for Internet IPv4 Path Most Common Operation Involving Hashing: HMAC

30 Cumulative Distribution of Packet Sizes

31 Multiple Packets Available for Parallel Processing

32 Data Stream Data Stream k..... Parallel Processing

33 Pipelining H + R 1 IV K t W t H R 2 step t, stage 1 step t, stage 2 Stage 1 Stage 2

Project 2 Project I (in groups of two or individually, 30% of grade) Modular Exponentiation of Large Integers Final report due Monday, May 9 Investigation of alternative architectures for the best performance in terms of Latency Latency x Area product in Xilinx FPGAs (Virtex 5 & Virtex 6) Altera FPGAs (Stratix III & Stratix IV) ASICs (bonus)

Primary applications (1) Execution units of general purpose microprocessors Integer units Floating point units Integers (8, 16, 32, 64 bits) Real numbers (32, 64 bits)

Primary applications (2) Digital signal and digital image processing Real or complex numbers (fixed-point or floating point) e.g., digital filters Discrete Fourier Transform Discrete Hilbert Transform General purpose DSP processors Specialized circuits

Primary applications (3) Coding Elements of the Galois fields GF(2 n ) (4-64 bits) Error detection codes Error correcting codes

Secret-key (Symmetric) Cryptosystems key of Alice and Bob - K AB Alice Bob Network Encryption Decryption

Hash Function arbitrary length message hash function hash valueh(m) h m fixed length It is computationally infeasible to find such m and m’ that h(m)=h(m’)

Primary applications (4) Cryptography Integers (16, 32, 64 bits) IDEA, RC6, Mars, SHA-3 candidates Twofish, Rijndael, SHA-3 candidates Elements of the Galois field GF(2 n ) (4, 8 bits)

RC6 MARS Twofish MUL32, 2 x ROL32, S-box 9x32 Main operations Auxiliary operations XOR, ADD/SUB32 2 x SQR32, 2 x ROL32 XOR, ADD/SUB32 96 S-box 4x4, 24 MUL GF(2 8 ) XOR ADD32 Rijndael Serpent 8 x 32 S-box 4x4 XOR 16 S-box 8x8 24 MUL GF(2 8 ) XOR

42 Basic Operations of 14 SHA-3 Candidates 42 NTT – Number Theoretic Transform, GF MUL – Galois Field multiplication, MUL – integer multiplication, mADDn – multioperand addition with n operands

Public Key (Asymmetric) Cryptosystems Public key of Bob - K B Private key of Bob - k B Alice Bob Network Encryption Decryption

RSA as a trap-door one-way function M C = f(M) = M e mod N C M = f -1 (C) = C d mod N PUBLIC KEY PRIVATE KEY N = P  Q P, Q - large prime numbers e  d  1 mod ((P-1)(Q-1))

RSA keys PUBLIC KEY PRIVATE KEY { e, N } { d, P, Q } N = P  Q e  d  1 mod ((P-1)(Q-1)) P, Q - large prime numbers

Primary applications (5) Cryptography Long integers (1k-16k bits) Public key cryptography RSA, DSA, Diffie-Hellman Elliptic Curve Cryptosystems Elements of the Galois field GF(2 n ) ( bits)

Primary applications (5) Cipher Breaking Public key cryptography RSA PUBLIC KEY RSA PRIVATE KEY { e, N } { d, P, Q } N = P  Q P, Q e  d  1 mod ((P-1)(Q-1))