Chapter 5B: Hardware/Software Codesign / Partitioning EECE **** Embedded System Design

- 2 - Universität Dortmund Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science Hardware/Software Codesign

- 3 - Universität Dortmund Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science Hardware/software partitioning  Functionality to be implemented in software or in hardware? No need to consider special purpose hardware in the long run? Correct for fixed functionality, but wrong in general, since “By the time MPEG-n can be implemented in software, MPEG-n+1 has been invented” [de Man]

- 4 - Universität Dortmund Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science Functionality to be implemented in software or in hardware? Decision based on hardware/ software partitioning, a special case of hardware/ software codesign.

- 5 - Universität Dortmund Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science Hardware/software codesign: approach Processor P1 Processor P2 Hardware Specification Mapping

- 6 - Universität Dortmund Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science An IP model for HW/SW partitioning Notation: Index set I denotes task graph nodes. Index set L denotes task graph node types e.g. square root, DCT or FFT Index set KH denotes hardware component types. e.g. hardware components for the DCT or the FFT. Index set J of hardware component instances Index set KP denotes processors. All processors are assumed to be of the same type Notation: Index set I denotes task graph nodes. Index set L denotes task graph node types e.g. square root, DCT or FFT Index set KH denotes hardware component types. e.g. hardware components for the DCT or the FFT. Index set J of hardware component instances Index set KP denotes processors. All processors are assumed to be of the same type

- 7 - Universität Dortmund Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science An IP model for HW/SW partitioning X i,k : =1 if node v i is mapped to hardware component type k  KH and 0 otherwise. Y i,k : =1 if node v i is mapped to processor k  KP and 0 otherwise. NY ℓ,k =1 if at least one node of type ℓ is mapped to processor k  KP and 0 otherwise. T is a mapping from task graph nodes to their types: T: I  L The cost function accumulates the cost of hardware units: C = cost(processors) + cost(memories) + cost(application specific hardware) X i,k : =1 if node v i is mapped to hardware component type k  KH and 0 otherwise. Y i,k : =1 if node v i is mapped to processor k  KP and 0 otherwise. NY ℓ,k =1 if at least one node of type ℓ is mapped to processor k  KP and 0 otherwise. T is a mapping from task graph nodes to their types: T: I  L The cost function accumulates the cost of hardware units: C = cost(processors) + cost(memories) + cost(application specific hardware)

- 8 - Universität Dortmund Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science Scheduling Processor p 1 ASIC h 1 FIR 1 FIR 2 v1v1 v2v2 v3v3 v4v4 v9v9 v 10 v 11 v5v5 v6v6 v7v7 v8v8 e3e3 e4e4 t p1p1 v8v8 v7v7 v7v7 v8v8 or... t c1c1 or... e3e3 e3e3 e4e4 e4e4 t FIR 2 on h 1 v4v4 v3v3 v3v3 v4v4 or... Communication channel c 1

- 9 - Universität Dortmund Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science Scheduling / precedence constraints For all nodes v i1 and v i2 that are potentially mapped to the same processor or hardware component instance, introduce a binary decision variable b i1,i2 with b i1,i2 =1 if v i1 is executed before v i2 and = 0 otherwise. Define constraints of the type (end-time of v i1 )  (start time of v i2 ) if b i1,i2 =1 and (end-time of v i2 )  (start time of v i1 ) if b i1,i2 =0 Ensure that the schedule for executing operations is consistent with the precedence constraints in the task graph. For all nodes v i1 and v i2 that are potentially mapped to the same processor or hardware component instance, introduce a binary decision variable b i1,i2 with b i1,i2 =1 if v i1 is executed before v i2 and = 0 otherwise. Define constraints of the type (end-time of v i1 )  (start time of v i2 ) if b i1,i2 =1 and (end-time of v i2 )  (start time of v i1 ) if b i1,i2 =0 Ensure that the schedule for executing operations is consistent with the precedence constraints in the task graph.

Universität Dortmund Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science Example HW types H1, H2 and H3 with costs of 20, 25, and 30. Processors of type P. Tasks T1 to T5. Execution times: HW types H1, H2 and H3 with costs of 20, 25, and 30. Processors of type P. Tasks T1 to T5. Execution times: TH1H2H3P

Universität Dortmund Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science Operation assignment constraints (1) TH1H2H3P X 1,1 +Y 1,1 =1 (task 1 mapped to H1 or to P) X 2,2 +Y 2,1 =1 X 3,3 +Y 3,1 =1 X 4,3 +Y 4,1 =1 X 5,1 +Y 5,1 =1

Universität Dortmund Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science Operation assignment constraints (2) Assume types of tasks are ℓ =1, 2, 3, 3, and 1.  ℓ  L,  i:T(v i )=c ℓ,  k  KP: NY ℓ,k  Y i,k Assume types of tasks are ℓ =1, 2, 3, 3, and 1.  ℓ  L,  i:T(v i )=c ℓ,  k  KP: NY ℓ,k  Y i,k Functionality 3 to be implemented on processor if node 4 is mapped to it.

Universität Dortmund Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science Other equations Time constraints leading to: Application specific hardware required for time constraints under 100 time units. TH1H2H3P Cost function: C=20 #(H1) + 25 #(H2) + 30 # (H3) + cost(processor) + cost(memory)

Universität Dortmund Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science Result For a time constraint of 100 time units and cost(P)<cost(H3): TH1H2H3P Solution (educated guessing) : T1  H1 T2  H2 T3  P T4  P T5  H1

Universität Dortmund Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science Separation of scheduling and partitioning Combined scheduling/partitioning very complex;  Heuristic: Compute estimated schedule Perform partitioning for estimated schedule Perform final scheduling If final schedule does not meet time constraint, go to 1 using a reduced overall timing constraint. Combined scheduling/partitioning very complex;  Heuristic: Compute estimated schedule Perform partitioning for estimated schedule Perform final scheduling If final schedule does not meet time constraint, go to 1 using a reduced overall timing constraint. 2 nd Iteration t specification Actual execution time 1 st Iteration approx. execution time t Actual execution time approx. execution time New specification

Universität Dortmund Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science Application example Audio lab (mixer, fader, echo, equalizer, balance units); slow SPARC processor 1µ ASIC library Allowable delay of µs (~ 44.1 kHz) Audio lab (mixer, fader, echo, equalizer, balance units); slow SPARC processor 1µ ASIC library Allowable delay of µs (~ 44.1 kHz) SPARC processor ASIC (Compass, 1 µ) External memory Outdated technology; just a proof of concept.

Universität Dortmund Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science Running time for COOL optimization  Only simple models can be solved optimally.

Universität Dortmund Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science Deviation from optimal design  Hardly any loss in design quality.

Universität Dortmund Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science Running time for heuristic

Universität Dortmund Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science Design space for audio lab Everything in software: 72.9 µs, 0 2 Everything in hardware: 3.06 µs, 457.9x Lowest cost for given sample rate: 18.6 µs, 78.4x10 6 2,

Universität Dortmund Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science Final remarks COOL approach:  shows that formal model of hardware/SW codesign is beneficial; IP modeling can lead to useful implementation even if optimal result is available only for small designs. Other approaches for HW/SW partitioning:  starting with everything mapped to hardware; gradually moving to software as long as timing constraint is met.  starting with everything mapped to software; gradually moving to hardware until timing constraint is met.  Binary search. COOL approach:  shows that formal model of hardware/SW codesign is beneficial; IP modeling can lead to useful implementation even if optimal result is available only for small designs. Other approaches for HW/SW partitioning:  starting with everything mapped to hardware; gradually moving to software as long as timing constraint is met.  starting with everything mapped to software; gradually moving to hardware until timing constraint is met.  Binary search.