IT 252 Computer Organization and Architecture Introduction Richard Helps (based on slides from Chia-Chi Teng)

What is computer architecture about? Computer architecture is the study of building computer systems. IT 252 is roughly split into four parts. – First, we will discusses instruction set architectures—the bridge between hardware and software. – Second, we introduce more advanced processor implementations. The focus is on pipelining, which is one of the most important ways to improve performance. – Next, we talk about memory systems, I/O, and how to connect it all together. – We will also introduce you to Assembly and C programming throughout the course.

Why should you care? It is interesting. – You will learn how a processor actually works! It will help you be a better system designer and integrator. – Understanding how your program is translated to assembly code lets you reason about correctness and performance. – Better understand the relationship between hardware and software – Demystify the seemingly arbitrary (e.g., bus errors, segmentation faults) Many cool jobs require an understanding of computer architecture. – The cutting edge is often pushing computers to their limits. – Supercomputing, games, portable devices, etc. Computer architecture illustrates many fundamental ideas in all computing discipline. – Abstraction, caching, and indirection …

Personnel  Lecturer —Prof. Richard Helps —Office hours W 12-2 PM Or by appointment  TA —Michael Zanandrea (Labs) —TBD (Homework) —TA Office hours F 12-1 PM in CTB 365, or by appointment  Course webpage:

Administrivia The textbooks provides the most comprehensive coverage – "Computer Systems: A Programmer's Perspective" 2nd Edition, by Randal E. Bryant & David R. O'Hallaron – The C Programming Language, Kernighan & Ritchie, 2 nd ed. Read the text prior to class class will supplement rather than regurgitate the text You need to do the reading. It will impact class discussion, homework, labs and tests

Grading Professionalism: Attendance, Attitude, Participation, 5% final grade Homework – Usually due on every Friday and Monday, check course website often for detail and update, 25% final grade Quizzes – about 8, in class, 10 pts each, 15% final grade No make-up, but drop lowest score. Lab reports – Due date to be specified by TA, 25% final grade Exams - final and at least one mid-term; usually open-book, take home, untimed 30%

Homework Homework exercises provide added impetus to keep up with the reading. Textbook problems plus other Assignments are listed on course web page by weeks, usually due on Monday of the following week. Turn in: on Gradebook We really want to encourage discussion, both in class and in lab. But zero tolerance for cheating, don’t go there. Don’t look for solutions online. HW1 due two weeks from today on 9/6, due to Labor day. Start early.

Labs  No lab this week. Lab 1 week of Sept.  Labs in Room 335  Lab report: TA will give you detail

To-Do list Read chapter 1 before Thursday Please read the entire course web thoroughly, today Course web is dynamic, please check back often IT 252 Gradebook check your daily (IT252 in subject line) keep up with the reading: this week … homework due – Check website (again, turn in on Gradebook & on paper) lab report due – TA discretion via Gradebook

What is Computer Architecture? It’s the study of the ___________ of computers  Structure: static arrangement of the parts  Organization: dynamic interaction of the parts and their control  Implementation: design of specific building blocks  Performance: behavioral study of the system or of some of its components 10/28/201510

Another definition: Instruction Set Architecture (ISA) Architecture is an interface between layers ISA is the interface between hardware and software ISA is what is visible to the programmer (and ISA might be different for OS and applications) ISA consists of: – instructions (operations and how they are encoded) – information units (size, how they are addressed etc.) – registers (or more generally processor state) – input-output control 10/28/201511

Computer structure: Von Neumann model 10/28/ Memory hierarchy I/OcontrolALU Registers PC state Memory bus I/O bus CPU Data path+ Control 1945

Computer Organization Organization and architecture often used as synonyms Organization (in this course) refers to: – what are the basic blocks of a computer system, more specifically basic blocks of the CPU basic blocks of the memory hierarchy – how are the basic blocks designed, controlled, connected? Organization used to be transparent to the ISA. Today more and more of the ISA is “exposed” to the user/compiler. 10/28/201513

Moore’s Law In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 24 months (i.e., grow exponentially with time). Amazingly visionary – million transistor/chip barrier was crossed in the 1980’s. – 2300 transistors, 1 MHz clock (Intel 4004) – 16 Million transistors (Ultra Sparc III) – 42 Million transistors, 2 GHz clock (Intel Xeon) – 2001 – 55 Million transistors, 3 GHz, 130nm technology, 250mm 2 die (Intel Pentium 4) – 140 Million transistors (HP PA-8500) – Today: 2.6 Billion transistors (10-core Xeon) –

Illustration of Moore’s Law

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Power Dissipation

Power Consumption: Watt/cm^2 

Evolution of Intel Microprocessor Speeds 10/28/ How about today?

Evolution of Microprocessor Speeds

POLL  Which type of CPU has the largest worldwide market share? —Intel —AMD —ARM —MIPS  e_choice_polls/LTE2OTY2MjI e_choice_polls/LTE2OTY2MjI

Where is the Market? Millions of Computers

Today’s Market  Embedded: 15 billion+ devices  Desktop/Laptop: 900 million to 1 billion  Servers: Unknown specific but at least 3 million in the world, not including virtual  Sources from Intel, AMD, GE, and other.

Impacts of Advancing Technology Processor – logic capacity:increases about 30% per year – performance:2x every 1.5 years Memory – DRAM capacity:4x every 3 years, now 2x every 2 years – memory speed:1.5x every 10 years – cost per bit:decreases about 25% per year Disk – capacity:increases about 60% per year ClockCycle = 1/ClockRate 500 MHz ClockRate = 2 nsec ClockCycle 1 GHz ClockRate = 1 nsec ClockCycle 4 GHz ClockRate = 250 psec ClockCycle

Admin  Using the LS site

Example Machine Organization Typical workstation design target – 25% of cost on processor – 25% of cost on memory (minimum memory size) – Rest on I/O devices, power supplies, box CPU Computer Control Datapath MemoryDevices Input Output

PC Motherboard Closeup

Inside the Pentium 4 Processor Chip

Some Computer families Computers that have the same (or very similar) ISA – Compatibility of software between various implementations IBM – 704, 709, 70xx etc.. From 1955 till 1965 – 360, 370, 43xx, 33xx From 1965 to the present – Power PC DEC – PDP-11, VAX From 1970 till 1985 – Alpha (now Compaq, now HP) in 1990’s 10/28/201529

More computer families Intel – Early micros 40xx in early 70’s – x86 (086,…,486, Pentium, Pentium Pro, Pentium 3, Pentium 4) from 1980 on – IA-64 (Itanium) in 2001 SUN – Sparc, Ultra Sparc n MIPS-SGI – Mips 2000, 3000, 4400, from 1985 on – CISC vs RISC – Complex Instruction Set vs Reduced Instruction Set – What is an instruction? 10/28/201530

Where Are We Now? CS142 & 124 IT344 Operating Sys (if used)

Registers Registers are the “bricks” of the CPU Registers are an essential part of the ISA – Visible to the hardware and to the programmer Registers are – Used for high speed storage for operands. For example, if variables i,j are in registers ax,cx respectively add ax,cx # i = i + j – Easy to name (most computers have limited number of registers visible to the programmer) – Used for addressing memory 10/28/201532

Registers (ct’d) Not all registers are “equal ” – Some are special-purpose (e.g. program counter, stack pointer) – Some are used for integer and some for floating-point – Some have restricted use by convention – Orthogonal Instruction sets – When any instruction can apply to any register or any memory address the I.S. is called “orthogonal” – Most instruction sets are “mostly” orthogonal – Learning the bits that are not orthogonal (and why) is a significant part of computer architecture 10/28/201533

Memory system  Memory is a hierarchy of devices with faster and more expensive ones closer to CPU —Registers —Caches (hierarchy: on-chip, off-chip) —Main memory (DRAM) —Secondary memory (disks) 10/28/2015CSE378 Gen. Intro34

Information units  Basic unit is the bit (has value 0 or 1)  Bits are grouped together in units and operated on together: —Byte = 8 bits —Word = 2 or 4 bytes —Double word = 2 words —Etc.  Integer: usually 4 bytes  Note that word length depends on the architecture. —Architectures exist with 24-bit words and others. 10/28/2015CSE378 Gen. Intro35

Memory addressing Memory is an array of information units – Each unit has the same size – Each unit has its own address – Address of an unit and contents of the unit at that address are different 10/28/ address contents This content could be pointing to address ‘0’

Addressing In most of today’s computers, the basic unit that can be addressed is a byte. (how many bit is a byte?) – MIPS (and pretty much all CPU today) is byte addressable The address space is the set of all memory units that a program can reference – The address space is usually tied to the length of the registers – Intel 384/486/Pentium has 32-bit registers. Hence its basic address space is 2 32 = 4G bytes – MIPS has 32-bit registers. – Older micros (minis) had 16-bit registers, hence 2 16 = 64 KB address space (too small) – Some current (Intel CoreX, Alpha, Itanium, Sparc, Altheon) machines have 64-bit registers, hence an enormous address space (2 64 = 18 ExaBytes (10 18 )) 10/28/201537

Addressing words  Although machines are byte-addressable, 4 byte integers are the most commonly used units  Every 32-bit word starts at an address divisible by 4 10/28/ int at address 0 int at address 4 int at address 8

Big-endian vs. little-endian  Byte order within an int:  RS-232  Ethernet Frame 10/28/ Little-endian (we’ll use this) Big-endian Memory address 3 int #0 byte int #0

The CPU - Instruction Execution Cycle  The CPU executes a program by repeatedly following this cycle 1. Fetch the next instruction, say instruction i 2. Execute instruction i 3. Compute address of the next instruction, say j 4. Go back to step 1  Of course we’ll optimize this but it’s the basic concept 10/28/201540

What’s in an instruction? An instruction tells the CPU – the operation to be performed via the OPCODE – where to find the operands (source and destination) For a given instruction, the ISA specifies – what the OPCODE means (semantics) – how many operands are required and their types, sizes etc.(syntax) Operand is either – register (integer, floating-point, PC) – a memory address – a constant 10/28/201541