EE365 Adv. Digital Circuit Design Clarkson University Lecture #12 Registers and Counters

Topics Rissacher EE365Lect #12 Registers Counters

Multibit registers and latches 74x175 Rissacher EE365Lect #12

8-bit (octal) register 74x374 –3-state output Rissacher EE365Lect #12

Other octal registers 74x273 –asynchronous clear – Non-three state output 74x377 –clock enable –no tristate-buffer Rissacher EE365Lect #12

Octal latch 74x373 –Output enable –Latch-enable input “C” or “G” Register vs. latch, what’s the difference? –Register: edge-triggered behavior –Latch: output follows input when G is asserted Rissacher EE365Lect #12

Counters Any sequential circuit whose state diagram is a single cycle. RESET EN Rissacher EE365Lect #12

Rissacher EE365Lect #12

LSB MSB Synchronous counter Serial enable logic Rissacher EE365Lect #12

LSB MSB Synchronous counter Parallel enable logic Rissacher EE365Lect #12

74x163 MSI 4-bit counter Rissacher EE365Lect #12

74x163 internal logic diagram XOR gates embody the “T” function Mux-like structure for loading Rissacher EE365Lect #12

Counter operation Free-running  16 Count if ENP and ENT both asserted. Load if LD is asserted (overrides counting). Clear if CLR is asserted (overrides loading and counting). All operations take place on rising CLK edge. RCO is asserted if ENT is asserted and Count = 15. Rissacher EE365Lect #12

Free-running 4-bit ’163 counter “divide-by-16” counter Rissacher EE365Lect #12

Modified counting sequence Load 0101 (5) after Count = 15 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 5, 6, … “divide-by-11” counter Rissacher EE365Lect #12

Another way Clear after Count = 1010 (10) 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2, 3, … “modulo-11” or “divide-by-11” counter trick to save gate inputs Rissacher EE365Lect #12

Counting from 3 to 12 Rissacher EE365Lect #12

Cascading counters RCO (ripple carry out) is asserted in state 15, if ENT is asserted. Rissacher EE365Lect #12

Decoding binary-counter states Rissacher EE365Lect #12

Decoder waveforms Glitches may or may not be a concern. Rissacher EE365Lect #12

Glitch-free outputs Registered outputs delayed by one clock tick. We’ll show another way to get the same outputs later, using a shift register. Rissacher EE365Lect #12

Shift registers For handling serial data, such as RS-232 and modem transmission and reception, Ethernet links, etc. Serial-in, serial- out Rissacher EE365Lect #12

Serial-to-parallel conversion Use a serial- in, parallel- out shift register Rissacher EE365Lect #12

Parallel-to-serial conversion Use parallel- in, serial-out shift register mux Rissacher EE365Lect #12

Do both Parallel- in, parallel- out shift register Rissacher EE365Lect #12

“Universal” shift register 74x194 Shift left Shift right Load Hold Rissacher EE365Lect #12

One stage of ’194 Rissacher EE365Lect #12

Shift-register counters Ring counter Rissacher EE365Lect #12

Johnson counter “Twisted ring” counter Rissacher EE365Lect #12

LFSR counters Pseudo-random number generator 2 n - 1 states before repeating Same circuits used in CRC error checking in Ethernet networks, etc. Rissacher EE365Lect #12

Next time More Serial Clock Skew Synchronization Rissacher EE365Lect #12