1 CSE370, Lecture 19 Lecture 19 u Logistics n Lab 8 this week to be done in pairs íFind a partner before your lab period íOtherwise you will have to wait for a pairing which will slow you down n HW5 and HW6 solutions out today íGraded HW5 available at review session tomorrow n HW7 out today due Wednesday March 4 n Midterm 2 Wednesday íCovers material up to simple FSM íReview session tomorrow, 4:30 here, EEB 037 u Last lecture n Counter FSM design n General Finite State Machine Design í Vending machine example u Today n Moore/Mealy machines n Midterm 2 topics and logistics

2 CSE370, Lecture 19 The “WHY” slide u Moore/Mealy machines n There are two different ways to express the FSMs with respect to the output. Both have different advantages so it is good to know them.

3 CSE370, Lecture 19 Inputs Outputs Next State Current State output logic Next-state logic Generalized FSM model: Moore and Mealy u Combinational logic computes next state and outputs n Next state is a function of current state and inputs n Outputs are functions of íCurrent state (Moore machine) íCurrent state and inputs (Mealy machine)

4 CSE370, Lecture 19 Moore versus Mealy machines outputs state feedback inputs reg combinational logic for next state logic for outputs Moore machine Outputs are a function of current state Outputs change synchronously with state changes Mealy machine Outputs depend on state and on inputs Input changes can cause immediate output changes (asynchronous) inputsoutputs state feedback reg combinational logic for next state logic for outputs

5 CSE370, Lecture 19 Impacts start of the FSM design procedure n Counter-design procedure 1. State diagram 2. State-transition table 3. Next-state logic minimization 4. Implement the design n FSM-design procedure 1. State diagram 2. State-transition table 3. State minimization 4. State encoding 5. Next-state logic minimization 6. Implement the design

6 CSE370, Lecture 19 State Diagrams u Moore machine n Each state is labeled by a pair: state-name/output or state-name [output] u Mealy machine n Each transition arc is labeled by a pair: input-condition/output

7 CSE370, Lecture 19 DQ Q DQ Q A B clock out Example 10  01: Moore or Mealy? u Circuits recognize AB=10 followed by AB=01 n What kinds of machines are they? Moore Mealy

8 CSE370, Lecture 19 Example “01 or 10” detector: a Moore machine u Output is a function of state only n Specify output in the state bubble D/1 E/1 B/0 A/0 C/ reset currentnextcurrent resetinputstatestateoutput 1––A000AB001AC000BB001BD000CE001CC000DE101DC100EB101ED11––A000AB001AC000BB001BD000CE001CC000DE101DC100EB101ED1

9 CSE370, Lecture 19 Example “01 or 10” detector: a Mealy machine u Output is a function of state and inputs n Specify outputs on transition arcs currentnextcurrent resetinputstatestateoutput B A C 0/1 0/0 1/1 1/0 reset/0 1––A000AB001AC000BB001BC100CB101CC01––A000AB001AC000BB001BC100CB101CC0

10 CSE370, Lecture 19 Comparing Moore and Mealy machines u Moore machines + Safer to use because outputs change at clock edge – May take additional logic to decode state into outputs u Mealy machines + Typically have fewer states + React faster to inputs — don't wait for clock – Asynchronous outputs can be dangerous u We often design synchronous Mealy machines n Design a Mealy machine n Then register the outputs

11 CSE370, Lecture 19 Synchronous (registered) Mealy machine u Registered state and registered outputs n No glitches on outputs n No race conditions between communicating machines inputsoutputs state feedback reg combinational logic for next state logic for outputs reg

12 CSE370, Lecture 19 Example “=01”: Moore or Mealy? u Recognize AB = 01 n Mealy or Moore? Registered Mealy (actually Moore) Moore

13 CSE370, Lecture 19 Example: A parity checker u Serial input string n OUT=1 if odd # of 1s in input n OUT=0 if even # of 1s in input u Let’s do this for Moore and Mealy

14 CSE370, Lecture 19 Example: A parity checker 1. State diagram Moore Mealy 0/0 1/1 1/0 0/1

15 CSE370, Lecture 19 Example: A parity checker Present Input Next Present State State Output Even 0 Even0 Even 1 Odd0 Odd 0 Odd1 Odd 1 Even1 1. State-transition table Present Input Next Present State State Output Even 0 Even0 Even 1 Odd1 Odd 0 Odd1 Odd 1 Even0 Moore Mealy

16 CSE370, Lecture State minimization: Already minimized n Need both states (even and odd) n Use one flip-flop Example: A parity checker

17 CSE370, Lecture State encoding Present Input Next Present State State Output Assignment Even 0 Odd 1 Present Input Next Present State State Output Moore Mealy Example: A parity checker

18 CSE370, Lecture 19 Example: A parity checker 5. Next-state logic minimization n Assume D flip-flops n Next state = (present state) XOR (present input) 6. Implement the design CLK Input Output DQ Q CLK Input Current State DQ Q Output Moore Mealy

19 CSE370, Lecture 19 What was covered after midterm 1 u Combinational logic applications n PLAs/PALs n ROMs n Adders n Multi-level logic n Timing diagrams n Hazards ????

20 CSE370, Lecture 19 What was covered after midterm 1 u Sequential logic building blocks n Latches (R-S and D) n Flip-flops (D and T) n Latch and flip-flop timing (setup/hold time, prop delay) n Timing diagrams n Asynchronous inputs and metastability n Registers Remember that the last number was 1

21 CSE370, Lecture 19 What was covered after midterm 1 u Counters n Timing diagrams n Shift registers n Ring counters n State diagrams and state-transition tables n Counter design procedure 1. Draw a state diagram 2. Draw a state-transition table 3. Encode the next-state functions 4. Implement the design n Self-starting counters 1, 2, 3, 4, …

22 CSE370, Lecture 19 u Finite state machines n FSM design procedure 1.State diagram 2.State-transition table 3. State minimization 4. State encoding 5. Next-state logic minimization 6.Implement the design  No Mealy machines What was covered after midterm 1 The last coin was 25cents and already had 50cents deposited so let’s pop out a soda Don’ t expect to know a ton of FSM. Just understand what was presented in the lectures.

23 CSE370, Lecture 19 Midterm 2 logistics u 45 minutes long (starts 10:35) u Materials covered from n Lectures 9 to 18 (but not Sequential Verilog or Moore/Mealy) n HW 4, 5, and 6 u Closed book/notes, no calculator u Scratch papers provided u Just have your pencil/pen and eraser u Raise hand for questions (don’t walk to get help)