Counter Classification Count modulus (MOD) – total number of states in the counter sequence Counter triggering technique – positive edge or negative edge Frequency division characteristics Asynchronous – no common clock – OR Synchronous - common clock - operation

Asynchronous Counters

Waveform Diagram for counter

State Transition The counter has two flip-flops and two output bits, therefore it a two-stage counter.The input clock does not trigger both flip-flops, therefore it is an asynchronous counterThe J and K inputs are tied together as kept HIGH, so they are considered to be toggle flip-flipsThe flip-flops are positive edge triggeredThe waveform analysis reveals that Q0 is the LSB and that its frequency is ½ the input clock frequency. Furthermore, Q1 is the MSB and that its frequency is ¼ the input clock frequencyThe count sequence is 00,01,10,11 where the LSB is Q0. Thus it is a MOD-4 binary up counter

State transition diagram

Asynchronous counter design Specify the operational requirements – number of stages, modulus, trigger and characteristics.Graph the desired output waveforms.Determine the necessary output to use as the clock input to the following stager. Either the true or complemented out put could serve as the clocking signal.Verify the circuit through analysis and testing.