CYU / CSIE / Yu-Hua Lee / E- 1 數位邏輯 Digital Fundamentals Chapter 9 Counters.

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Presentation transcript:

CYU / CSIE / Yu-Hua Lee / E- 1 數位邏輯 Digital Fundamentals Chapter 9 Counters

CYU / CSIE / Yu-Hua Lee / E- 2 Chapter 9 Counters 9-1 Asynchronous Counter Operation 9-2 Synchronous Counter Operation 9-3 Up/Down Synchronous Counters 9-4 Design of Synchronous Counters 9-5 Cascaded Counters 9-6 Counter Decoding 9-7 Counter Applications 9-8 Troubleshooting 9-9 Logic Symbols with Dependency Notation 9-10 Programmable Logic

CYU / CSIE / Yu-Hua Lee / E- 3 Figure 9--1 A 2-bit asynchronous binary counter. Open file F09-01 to verify operation.

CYU / CSIE / Yu-Hua Lee / E- 4 Figure 9--2 Timing diagram for the counter of Figure 9-1. As in previous chapters, output waveforms are shown in green.

CYU / CSIE / Yu-Hua Lee / E- 5 Figure 9--3 Three-bit asynchronous binary counter and its timing diagram for one cycle. Open file F09-03 to verify operation.

CYU / CSIE / Yu-Hua Lee / E- 6 Figure 9--4 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.

CYU / CSIE / Yu-Hua Lee / E- 7 Figure 9--5 Four-bit asynchronous binary counter and its timing diagram. Open file F09-05 and verify the operation.

CYU / CSIE / Yu-Hua Lee / E- 8 Figure 9--6 An asynchronously clocked decade counter with asynchronous recycling.

CYU / CSIE / Yu-Hua Lee / E- 9 Figure 9--7 Asynchronously clocked modulus-12 counter with asynchronous recycling.

CYU / CSIE / Yu-Hua Lee / E- 10 Figure 9--8 The 74LS93A 4-bit asynchronous binary counter logic diagram. (Pin numbers are in parentheses, and all J and K inputs are internally connected HIGH.)

CYU / CSIE / Yu-Hua Lee / E- 11 Figure 9--9 Two configurations of the 74LS93A asynchronous counter. (The qualifying label, CTR DIV n, indicates a counter with n states.)

CYU / CSIE / Yu-Hua Lee / E- 12 Figure LS93A connected as a modulus-12 counter.

CYU / CSIE / Yu-Hua Lee / E- 13 Chapter 9 Counters 9-1 Asynchronous Counter Operation 9-2 Synchronous Counter Operation 9-3 Up/Down Synchronous Counters 9-4 Design of Synchronous Counters 9-5 Cascaded Counters 9-6 Counter Decoding 9-7 Counter Applications 9-8 Troubleshooting 9-9 Logic Symbols with Dependency Notation 9-10 Programmable Logic

CYU / CSIE / Yu-Hua Lee / E- 14 Figure A 2-bit synchronous binary counter.

CYU / CSIE / Yu-Hua Lee / E- 15 Figure Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-flops are assumed to be equal).

CYU / CSIE / Yu-Hua Lee / E- 16 Figure Timing diagram for the counter of Figure 9-11.

CYU / CSIE / Yu-Hua Lee / E- 17 Figure A 3-bit synchronous binary counter. Open file F09-14 to verify the operation.

CYU / CSIE / Yu-Hua Lee / E- 18 Figure Timing diagram for the counter of Figure 9-14.

CYU / CSIE / Yu-Hua Lee / E- 19 Figure A 4-bit synchronous binary counter and timing diagram. Points where the AND gate outputs are HIGH are indicated by the shaded areas.

CYU / CSIE / Yu-Hua Lee / E- 20 Figure A synchronous BCD decade counter. Open file F09-17 to verify operation.

CYU / CSIE / Yu-Hua Lee / E- 21 Figure Timing diagram for the BCD decade counter (Q 0 is the LSB).

CYU / CSIE / Yu-Hua Lee / E- 22 Figure The 74HC163 4-bit synchronous binary counter. (The qualifying label CTR DIV 16 indicates a counter with sixteen states.)

CYU / CSIE / Yu-Hua Lee / E- 23 Figure Timing example for a 74HC163.

CYU / CSIE / Yu-Hua Lee / E- 24 Figure The 74LS160 synchronous BCD decade counter. (The qualifying label CTR DIV 10 indicates a counter with ten states.)

CYU / CSIE / Yu-Hua Lee / E- 25 Figure Timing example for a 74LS160.

CYU / CSIE / Yu-Hua Lee / E- 26 Chapter 9 Counters 9-1 Asynchronous Counter Operation 9-2 Synchronous Counter Operation 9-3 Up/Down Synchronous Counters 9-4 Design of Synchronous Counters 9-5 Cascaded Counters 9-6 Counter Decoding 9-7 Counter Applications 9-8 Troubleshooting 9-9 Logic Symbols with Dependency Notation 9-10 Programmable Logic

CYU / CSIE / Yu-Hua Lee / E- 27 Figure A basic 3-bit up/down synchronous counter. Open file F09-23 to verify operation.

CYU / CSIE / Yu-Hua Lee / E- 28 Figure 9--24

CYU / CSIE / Yu-Hua Lee / E- 29 Figure The 74HC190 up/down synchronous decade counter.

CYU / CSIE / Yu-Hua Lee / E- 30 Figure Timing example for a 74HC190.

CYU / CSIE / Yu-Hua Lee / E- 31 Chapter 9 Counters 9-1 Asynchronous Counter Operation 9-2 Synchronous Counter Operation 9-3 Up/Down Synchronous Counters 9-4 Design of Synchronous Counters 9-5 Cascaded Counters 9-6 Counter Decoding 9-7 Counter Applications 9-8 Troubleshooting 9-9 Logic Symbols with Dependency Notation 9-10 Programmable Logic

CYU / CSIE / Yu-Hua Lee / E- 32 Figure General clocked sequential circuit.

CYU / CSIE / Yu-Hua Lee / E- 33 Figure State diagram for a 3-bit Gray code counter.

CYU / CSIE / Yu-Hua Lee / E- 34 Figure Examples of the mapping procedure for the counter sequence represented in Table 9-7 and Table 9-8.

CYU / CSIE / Yu-Hua Lee / E- 35 Figure Karnaugh maps for present-state J and K inputs.

CYU / CSIE / Yu-Hua Lee / E- 36 Figure Three-bit Gray code counter. Open file F09-31 to verify operation.

CYU / CSIE / Yu-Hua Lee / E- 37 Figure 9--32

CYU / CSIE / Yu-Hua Lee / E- 38 Figure 9--33

CYU / CSIE / Yu-Hua Lee / E- 39 Figure 9--34

CYU / CSIE / Yu-Hua Lee / E- 40 Figure State diagram for a 3-bit up/down Gray code counter.

CYU / CSIE / Yu-Hua Lee / E- 41 Figure J and K maps for Table The UP/DOWN control input, Y, is treated as a fourth variable.

CYU / CSIE / Yu-Hua Lee / E- 42 Figure Three-bit up/down Gray code counter.

CYU / CSIE / Yu-Hua Lee / E- 43 Chapter 9 Counters 9-1 Asynchronous Counter Operation 9-2 Synchronous Counter Operation 9-3 Up/Down Synchronous Counters 9-4 Design of Synchronous Counters 9-5 Cascaded Counters 9-6 Counter Decoding 9-7 Counter Applications 9-8 Troubleshooting 9-9 Logic Symbols with Dependency Notation 9-10 Programmable Logic

CYU / CSIE / Yu-Hua Lee / E- 44 Figure Two cascaded counters (all J and K inputs are HIGH).

CYU / CSIE / Yu-Hua Lee / E- 45 Figure Timing diagram for the cascaded counter configuration of Figure 9-38.

CYU / CSIE / Yu-Hua Lee / E- 46 Figure A modulus-100 counter using two cascaded decade counters.

CYU / CSIE / Yu-Hua Lee / E- 47 Figure Three cascaded decade counters forming a divide-by-1000 frequency divider with intermediate divide- by-10 and divide-by-100 outputs.

CYU / CSIE / Yu-Hua Lee / E- 48 Figure 9--42

CYU / CSIE / Yu-Hua Lee / E- 49 Figure A divide-by-100 counter using two 74LS160 decade counters.

CYU / CSIE / Yu-Hua Lee / E- 50 Figure A divide-by-40,000 counter using 74HC161 4-bit binary counters. Note that each of the parallel data inputs is shown in binary order (the right-most bit D 0 is the LSB in each counter).

CYU / CSIE / Yu-Hua Lee / E- 51 Chapter 9 Counters 9-1 Asynchronous Counter Operation 9-2 Synchronous Counter Operation 9-3 Up/Down Synchronous Counters 9-4 Design of Synchronous Counters 9-5 Cascaded Counters 9-6 Counter Decoding 9-7 Counter Applications 9-8 Troubleshooting 9-9 Logic Symbols with Dependency Notation 9-10 Programmable Logic

CYU / CSIE / Yu-Hua Lee / E- 52 Figure Decoding of state 6 (110). Open file F09-45 to verify operation.

CYU / CSIE / Yu-Hua Lee / E- 53 Figure A 3-bit counter with active-HIGH decoding of count 2 and count 7. Open file F09-46 to verify operation.

CYU / CSIE / Yu-Hua Lee / E- 54 Figure A basic decade (BCD) counter and decoder.

CYU / CSIE / Yu-Hua Lee / E- 55 Figure Outputs with glitches from the decoder in Figure Glitch widths are exaggerated for illustration and are usually only a few nanoseconds wide.

CYU / CSIE / Yu-Hua Lee / E- 56 Figure The basic decade counter and decoder with strobing to eliminate glitches.

CYU / CSIE / Yu-Hua Lee / E- 57 Figure Strobed decoder outputs for the circuit of Figure 9-49.

CYU / CSIE / Yu-Hua Lee / E- 58 Chapter 9 Counters 9-1 Asynchronous Counter Operation 9-2 Synchronous Counter Operation 9-3 Up/Down Synchronous Counters 9-4 Design of Synchronous Counters 9-5 Cascaded Counters 9-6 Counter Decoding 9-7 Counter Applications 9-8 Troubleshooting 9-9 Logic Symbols with Dependency Notation 9-10 Programmable Logic

CYU / CSIE / Yu-Hua Lee / E- 59 Figure Simplified logic diagram for a 12-hour digital clock. Logic details using specific devices are shown in Figures 9-52 and 9-53.

CYU / CSIE / Yu-Hua Lee / E- 60 Figure Logic diagram of typical divide-by-60 counter using 74LS160A synchronous decade counters. Note that the outputs are in binary order (the right-most bit is the LSB).

CYU / CSIE / Yu-Hua Lee / E- 61 Figure Logic diagram for hours counter and decoders. Note that on the counter inputs and outputs, the right-most bit is the LSB.

CYU / CSIE / Yu-Hua Lee / E- 62 Figure Functional block diagram for parking garage control.

CYU / CSIE / Yu-Hua Lee / E- 63 Figure Logic diagram for modulus-100 up/down counter for automobile parking control.

CYU / CSIE / Yu-Hua Lee / E- 64 Figure Parallel-to-serial data conversion logic.

CYU / CSIE / Yu-Hua Lee / E- 65 Figure Example of parallel-to-serial conversion timing for the circuit in Figure 9-56.

CYU / CSIE / Yu-Hua Lee / E- 66 Chapter 9 Counters 9-1 Asynchronous Counter Operation 9-2 Synchronous Counter Operation 9-3 Up/Down Synchronous Counters 9-4 Design of Synchronous Counters 9-5 Cascaded Counters 9-6 Counter Decoding 9-7 Counter Applications 9-8 Troubleshooting 9-9 Logic Symbols with Dependency Notation 9-10 Programmable Logic

CYU / CSIE / Yu-Hua Lee / E- 67 Figure Example of a failure that affects following counters in a cascaded arrangement.

CYU / CSIE / Yu-Hua Lee / E- 68 Figure Example of a failure in a cascaded counter with a truncated sequence.

CYU / CSIE / Yu-Hua Lee / E- 69 Figure 9--60

CYU / CSIE / Yu-Hua Lee / E- 70 Figure 9--61

CYU / CSIE / Yu-Hua Lee / E- 71 Chapter 9 Counters 9-1 Asynchronous Counter Operation 9-2 Synchronous Counter Operation 9-3 Up/Down Synchronous Counters 9-4 Design of Synchronous Counters 9-5 Cascaded Counters 9-6 Counter Decoding 9-7 Counter Applications 9-8 Troubleshooting 9-9 Logic Symbols with Dependency Notation 9-10 Programmable Logic

CYU / CSIE / Yu-Hua Lee / E- 72 Figure The 74HC163 4-bit synchronous counter.

CYU / CSIE / Yu-Hua Lee / E- 73 Chapter 9 Counters 9-1 Asynchronous Counter Operation 9-2 Synchronous Counter Operation 9-3 Up/Down Synchronous Counters 9-4 Design of Synchronous Counters 9-5 Cascaded Counters 9-6 Counter Decoding 9-7 Counter Applications 9-8 Troubleshooting 9-9 Logic Symbols with Dependency Notation 9-10 Programmable Logic

CYU / CSIE / Yu-Hua Lee / E- 74 Figure Combinational mode for active-LOW and active-HIGH outputs. The red lines show the logic paths in each case.

CYU / CSIE / Yu-Hua Lee / E- 75 Figure Registered mode for active-LOW and active-HIGH outputs. The red lines show the logic paths in each case.

CYU / CSIE / Yu-Hua Lee / E- 76 Figure 9--65

CYU / CSIE / Yu-Hua Lee / E- 77 數位邏輯 Digital Fundamentals Chapter 9 Counters Digital System Application

CYU / CSIE / Yu-Hua Lee / E- 78 Figure Traffic light control system block diagram and light sequence.

CYU / CSIE / Yu-Hua Lee / E- 79 Figure Block diagram of the sequential logic.

CYU / CSIE / Yu-Hua Lee / E- 80 Figure State diagram showing the 2-bit Gray code sequence.

CYU / CSIE / Yu-Hua Lee / E- 81 Figure Sequential logic.

CYU / CSIE / Yu-Hua Lee / E- 82 Figure 9--70

CYU / CSIE / Yu-Hua Lee / E- 83 Figure 9--71

CYU / CSIE / Yu-Hua Lee / E- 84 Figure 9--72

CYU / CSIE / Yu-Hua Lee / E- 85 Figure Comparison of asynchronous and synchronous counters.

CYU / CSIE / Yu-Hua Lee / E- 86 Figure Note that the labels (names of inputs and outputs) are consistent with text but may differ from the particular manufacturer ’ s data book you are using. The devices shown are functionally the same and pin compatible with the same device types in other available TTL and CMOS IC families.

CYU / CSIE / Yu-Hua Lee / E- 87 數位邏輯 Digital Fundamentals Chapter 9 Counters PROBLEMS

CYU / CSIE / Yu-Hua Lee / E- 88 Figure 9--75

CYU / CSIE / Yu-Hua Lee / E- 89 Figure 9--76

CYU / CSIE / Yu-Hua Lee / E- 90 Figure 9--77

CYU / CSIE / Yu-Hua Lee / E- 91 Figure 9--78

CYU / CSIE / Yu-Hua Lee / E- 92 Figure 9--79

CYU / CSIE / Yu-Hua Lee / E- 93 Figure 9--80

CYU / CSIE / Yu-Hua Lee / E- 94 Figure 9--81

CYU / CSIE / Yu-Hua Lee / E- 95 Figure 9--82

CYU / CSIE / Yu-Hua Lee / E- 96 Figure 9--83

CYU / CSIE / Yu-Hua Lee / E- 97 Figure 9--84

CYU / CSIE / Yu-Hua Lee / E- 98 Figure 9--85

CYU / CSIE / Yu-Hua Lee / E- 99 Figure 9--86

CYU / CSIE / Yu-Hua Lee / E- 100 Figure 9--87

CYU / CSIE / Yu-Hua Lee / E- 101 Figure 9--88

CYU / CSIE / Yu-Hua Lee / E- 102 Figure 9--89

CYU / CSIE / Yu-Hua Lee / E- 103 Figure 9--90

CYU / CSIE / Yu-Hua Lee / E- 104 Figure 9--91

CYU / CSIE / Yu-Hua Lee / E- 105 Figure 9--92

CYU / CSIE / Yu-Hua Lee / E- 106 Figure 9--93

CYU / CSIE / Yu-Hua Lee / E- 107 Figure 9--94

CYU / CSIE / Yu-Hua Lee / E- 108 Figure 9--95

CYU / CSIE / Yu-Hua Lee / E- 109 Figure 9--96

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