Digital Logic Design Lecture # 21 University of Tehran

Outline Counter Designing a Garage Door Opener

Counter Counters are structures that are basically simple state machines. Let’s design a binary up-down counter (modulo 4), as shown in this figure, that will count up when clocked with u=1 and count down otherwise.

Counter (continued…) The state diagram and the state table:

Counter (continued…) Note that we can do state assignment in any particular form we like, here we have done our state assignment based on the outputs of the circuit. Considering that we want to use D flip flops, so the transition table and the excitation table are the same.

Counter (continued…) Now we can easily derive KMs and the circuit:

Counter (continued…) As you can see, no extra logic is needed for the outputs because we based our state assignment on our outputs. In problems such as the above we can skip some of the steps of sequential circuit design such as the state diagram and the state table because of the fairly straight forward nature of the problem description.

Counter (continued…) Consider the following modulo 5 counter design:

Counter (continued…) In such cases, the KMs can be easily drawn, because for instance the state after 000 is 001, so we place 0, 0 and 1 in the 000 square of respective KMs. The circuit:

Counter (continued…) In problem such as the above unwanted states are an important issue. For instance in this circuit we have 101, 010 and 110 as three unwanted states. Now if the circuit powers up into an unwanted state we must analyze the circuit to see what happens. This analysis can be done by either looping through the circuit or using the KMs. For instance in this circuit we will have (considering mapped don’t cares as 1s and unmapped ones as 0s): 101    010

Counter (continued…) We can usually tolerate unwanted states at power up if we are lead back into the circuit’s course after one clock pulse. This is not always the case as in the 110 state in the last example. In such cases or if we don’t want unwanted states to occur, one of the following measures can be applied: Use asynchronous set and reset as shown in the figure for this circuit. Use fixed mapping. Meaning that we forget using don’t cares in our mapping.

Counter (continued…) Repair after mapping. Meaning that we change the mappings of our circuit in order to always enter the wanted sequence after at most one clock pulse. In our example for instance we could map 101 and 100 instead of 100 and 110. Insert synchronous set and reset. This is done when asynchronous set and reset features are not available in our flip flops. Thus we can no longer override the clock and we have to add gates outside the flip flop to clear or set the flip flops value at clock pulse time:

Counter (continued…) With this solution we can redraw our design:

Counter (continued…) As a historic comment, we must mention ASM (Arithmetic State Machine) that were used historically to design state machines, but nowadays Verilog coding can be easily used instead.

Designing a Garage Door Opener Now we will see a larger design of a garage door opener.

Designing a Garage Door Opener (continued…) As a problem description, it must be said that we use a remote control with a push button that will open and close the door once pushed, changing between close and open every time it’s pressed. The door will roll completely up or completely down if not blocked. There are sensors that will sends signals to show when the door is completely down or up, another signal will also inform us when the path of the door has become blocked. Thus we will have four input signals to our system named P (Push button), U (up), D (Down) and B (Blocked).

Designing a Garage Door Opener (continued…) Our system will have three output signals to control the door O (Open), C (Close), H (Halt). The last signal occurs when something has gone badly wrong in our system and repairing is needed like when both U and D are 1. Note: Outputs O and C aren’t necessarily complements because when we don’t want the door to move, both outputs must be 0. To construct our state machine we’ll consider the following basic form for our nodes:

Designing a Garage Door Opener (continued…)

The following scenarios have been considered in our state machine: If anything gets in the path of the door when opening, nothing will happen and the door opens. When the door is closing if something appears in it’s path then B=1. When the door is opening, pressing the button will cause it to stop, and the user will have to press the button again in order to close it. HLTC (Halt During Close) is a state where the door stops moving and we know that we will be going to the opening state afterwards.

Designing a Garage Door Opener (continued…) We have considered 4 inputs for each state and thus 16 different combinations but all combinations will never be detected thus aren’t issued. An emergency state can also be considered where everything will halt and an emergency light put on. A starting state must be considered for the system at power on. For instance the door must be completely closed at the beginning.