IO CONNECTION ASSIGNMENT AND RDL ROUTING FOR FLIP-CHIP DESIGNS Jin-Tai Yan, Zhi-Wei Chen 1 ASPDAC.2009.

Outline  Introduction  Problem Formulation  IO Connection Assignment for Flip-Chip Designs  RDL Routing for Flip-Chip Designs  Experimental Results  Conclusions 2

Introduction 3  As the circuit complexity increases and the feature size decreases, flip-chip (FC) package is introduced to meet the higher integration density and the larger I/O counts of modern VLSI circuits.  However, the placement of the I/O pads in IC designs is not well mapped onto the bump balls in flip-chip designs.

Introduction 4  Hence, an extra metal layer, Re-Distribution Layer (RDL), is used to redistribute the IO pads to the bump balls without changing the placement of the IO pads.

Problem Formulation 5 1. In general, RDL routing in flip-chip designs is only allowed to route all the connections in a single layer. 2. Two-pin net or multiple-pin net. 3. The capacity constraints between any pair of adjacent bump balls. 4. Minimize the total wirelength. Wire Crossing

IO Connection Assignment for Flip-Chip Designs 6  capacity constraint : 2

Algorithm Preview 7  Two-phase routing approach

IO Connection Assignment for Flip-Chip Designs 8  Find the Delaunay triangulation for IO buffers

IO Connection Assignment for Flip-Chip Designs 9  Find the Voronoi diagram for IO buffers

IO Connection Assignment for Flip-Chip Designs 10  The IO buffer in any Voronoi polygon containing at least one IO ball can be assigned onto the closer IO ball inside the Voronoi polygon.

IO Connection Assignment for Flip-Chip Designs 11  Delete the connected IO buffer and balls and constructed a new Voronoi diagram using the remaining IO buffers. And assign IO buffer to IO ball again.

IO Connection Assignment for Flip-Chip Designs 12

Algorithm 13  Two-phase routing approach

IO Connection Assignment for Flip-Chip Designs 14  For increasing the routability, exchanged a pair of IO connections by using the pair-exchange operation.  For routability  For wirelength

IO Connection Assignment for Flip-Chip Designs 15

Algorithm 16  Two-phase routing approach

IO Connection Assignment for Flip-Chip Designs 17  The IO ball which is the closest to the geometrical center of all the IO buffers is selected as the common IO ball of the set of IO buffers with the same number.

Algorithm 18  Two-phase routing approach

RDL Routing for Flip-Chip Designs 19  In the global wire assignment, the routing regions of all the IO connections in a routing plane can be easily constructed.

RDL Routing for Flip-Chip Designs 20  Global wire assignment  The global wire of the IO connection will be assigned as a global feasible path through the covered edges inside its routing region under the capacity constraint by the probabilistic congestion control[7].

RDL Routing for Flip-Chip Designs 21  Steiner-point assignment  The two global wires located in the same quadrants or adjacent quadrant may assign a Steiner point to reduce the total wirelength.

RDL Routing for Flip-Chip Designs 22

Algorithm 23  Two-phase routing approach

RDL Routing for Flip-Chip Designs 24  Crossing-point assignment  If the capacity constraint inside a passing edge is satisfied, the crossing point of any global wire inside a passing edge must be further assigned.

RDL Routing for Flip-Chip Designs 25  River routing for physical path assignment  According to the result of the crossing-point assignment, the physical paths of the two-terminal connections can be routed by using a river routing algorithm

RDL Routing for Flip-Chip Designs 26  Maze routing  The physical paths of the unassigned IO connections can be further obtained by running a maze-routing algorithm

Algorithm Review 27

Experimental Results 28  Six tested circuits with random locations of IO buffers are generated.  For the comparison of the routing result:  a greedy IO connection assignment approach  a single-layer BGA global router[8]

Conclusions 29  This paper propose an O(n 2 ) IO assignment and RDL routing algorithm and guarantee 100% routability if the capacity constraint is permitted.  The experimental results show that our RDL routing algorithm is very effective for flip-chip designs.