Tackling the search for Lepton Flavor Violation with GHz waveform digitizing using the DRS chip Stefan Ritt Paul Scherrer Institute, Switzerland

Feb. 26th, 2008Fermilab2 Agenda DRS2 DRS3 DRS1 MEG Experiment searching for  e  down to MEG Experiment searching for  e  down to

Motivation Why should we search for  e  ?

Feb. 26th, 2008Fermilab4 The Standard Model Fermions (Matter) Quarks u up c charm t top d down s strange b bottom Leptons e electron neutrino  muon neutrino  tau neutrino e electron  muon  tau Bosons  photon Force carriers g gluon W W boson Z Z boson Higgs* boson *) Yet to be confirmed Generation I II III

Feb. 26th, 2008Fermilab5 The success of the SM The SM has been proven to be extremely successful since 1970’s Simplicity (6 quarks explain >40 mesons and baryons) Explains all interactions in current accelerator particle physics Predicted many particles (most prominent W, Z ) Limitations of the SM Currently contains 19 (+10) free parameters such as particle (neutrino) masses Does not explain cosmological observation such as Dark Matter and Matter/Antimatter Asymmetry CDF Today’s goal is to look for physics beyond the standard model

Feb. 26th, 2008Fermilab6 Beyond the SM Find New Physics Beyond the SM High Energy Frontier Produce heavy new particles directly Heavy particles need large colliders Complex detectors High Precision Frontier Look for small deviations from SM (g-2) , CKM unitarity Look for forbidden decays Requires high precision at low energy

Feb. 26th, 2008Fermilab7 Discovery: 1936 in cosmic radiation Mass: 105 MeV/c 2 Mean lifetime: 2.2  s The Muon Seth Neddermeyer Carl Anderson e --  W-W- e-e- ≈ 100% < led to Lepton Flavor Conservation as “accidental” symmetry

Feb. 26th, 2008Fermilab8 LFV and Neutrino Oscillations Neutrino Oscillations  Neutrino mass   e  possible even in the SM  W-W-   e e-e-  LFV in the charged sector is forbidden in the Standard Model mixing

Feb. 26th, 2008Fermilab9 LFV in SUSY While LFV is forbidden in SM, it is possible in SUSY  W-W-   e e-e-   e-e- ≈ Current experimental limit: BR(   e  ) <

Feb. 26th, 2008Fermilab10 History of LFV searches Long history dating back to 1947! Best present limits: 1.2 x (MEGA)  Ti → eTi < 7 x (SINDRUM II)  → eee < 1 x (SINDRUM II) MEG Experiment aims at Improvements linked to advance in technology  → e   → eA  → eee MEG SUSY SU(5) BR(   e  ) =   Ti  eTi = 4x  BR(   eee) = 6x SUSY SU(5) BR(   e  ) =   Ti  eTi = 4x  BR(   eee) = 6x cosmic  stopped   beams stopped 

Feb. 26th, 2008Fermilab11 Current SUSY predictions “Supersymmetric parameterspace accessible by LHC” W. Buchmueller, DESY, priv. comm. current limit MEG goal 1)J. Hisano et al., Phys. Lett. B391 (1997) 341 2)MEGA collaboration, hep-ex/ f t (M)=2.4  >0 M l =50GeV 1) tan 

Experimental Method How to detect  e  ?

Feb. 26th, 2008Fermilab13 Decay topology  e  e     e  180º  → e  signal very clean E g = E e = 52.8 MeV   e = 180º e and  in time 52.8 MeV E  [MeV] N 52.8 MeV E e [MeV] N 52.8 MeV

Feb. 26th, 2008Fermilab14 “Accidental” Background e     e  180º  → e  signal very clean E g = E e = 52.8 MeV   e = 180º e and  in time e    e e    e Annihilation in flight Background Good energy resolution Good spatial resolution Excellent timing resolution Good pile-up rejection

Feb. 26th, 2008Fermilab15 Previous Experiments Exp./ Lab AuthorYear  E e /E e %FWHM  E  /E  %FWHM  t e  (ns)  e  (mrad) Inst. Stop rate (s -1 ) Duty cycle (%) Result SIN (PSI) A. Van der Schaaf (4..6) x < 1.0  TRIUMF P. Depommier x < 3.6  LANL W.W. Kinnison x < 1.7  Crystal Box R.D. Bolton x 10 5 (6..9) < 4.9  MEGAM.L. Brooks x 10 8 (6..7) < 1.2  MEG?????? ~ How can we achieve a quantum step in detector technology?

Feb. 26th, 2008Fermilab16 Collaboration ~70 People (40 FTEs) from five countries

Feb. 26th, 2008Fermilab17 Paul Scherrer Institute Swiss Light Source Proton Accelerator

Feb. 26th, 2008Fermilab18 PSI Proton Accelerator

Feb. 26th, 2008Fermilab19 MEG beam line ++ R  ~ 1.1x10 8  + /s at experiment  ~ 10.9 mm e+e+ ++

Feb. 26th, 2008Fermilab20 Liquid Xenon Calorimeter Calorimeter: Measure  Energy, Position and Time through scintillation light only Liquid Xenon has high Z and homogeneity ~900 l (3t) Xenon with 848 PMTs (quartz window, immersed) Cryogenics required: -120°C … -108° Extremely high purity necessary: 1 ppm H 2 0 absorbs 90% of light Currently largest LXe detector in the world: Lots of pioneering work necessary  

Feb. 26th, 2008Fermilab21 Use GEANT to carefully study detector Optimize placement of PMTs according to MC results

Feb. 26th, 2008Fermilab22 The complete MEG detector

Feb. 26th, 2008Fermilab23 Current resolution estimates Exp./ Lab AuthorYear  E e /E e %FWH M  E  /E  %FWHM  t e  (ns)  e  (mrad) Inst. Stop rate (s -1 ) Duty cycle (%) Result SIN (PSI) A. Van der Schaaf (4..6) x < 1.0  TRIUMF P. Depommier x < 3.6  LANL W.W. Kinnison x < 1.7  Crystal Box R.D. Bolton x 10 5 (6..9) < 4.9  MEGAM.L. Brooks x 10 8 (6..7) < 1.2  MEG x ~

Feb. 26th, 2008Fermilab24 MEG Current Status Goal: Produce “significant” result before LHC R & D phase took longer than anticipated Detector has been completed by the end of 2007 Expected sensitivity in 2008: 2 x (current limit: 1 x ) R&D Engineering Data Taking Set-up

Feb. 26th, 2008Fermilab25 Pile-up in the DC system Pile-up can severely degrade the experiment performance (  MEGA Experiment) ! Traditional electronics cannot detect pile-up TDC Amplifier DiscriminatorMeasure Time Need full waveform digitization > 100 MHz to reject pile-up Need full waveform digitization > 100 MHz to reject pile-up Moving average baseline hits

Feb. 26th, 2008Fermilab26 Beam induced background 10 8  /s produce 10 8 e + /s produce 10 8  /s Cable ducts for Drift Chamber

Feb. 26th, 2008Fermilab27 Pile-up in the LXe calorimeter n E[MeV] ee radiative muon decay t PMT sum e   (  e ) 2 +  e  51.5 MeV MeV  ’s hitting different parts of LXe can be separated if > 2 PMTs apart (15 cm) Timely separated  ’s need waveform digitizing > 300 MHz If waveform digitizing gives timing <100ps, no TDCs are needed  ’s hitting different parts of LXe can be separated if > 2 PMTs apart (15 cm) Timely separated  ’s need waveform digitizing > 300 MHz If waveform digitizing gives timing <100ps, no TDCs are needed ~100ns

Feb. 26th, 2008Fermilab28 Need 500 MHz 12 bit digitization for Drift Chamber system Need 2 GHz 12 bit digitization for Xenon Calorimeter + Timing Counters Need 3000 Channels At affordable price Requirements summary Solution: Develop own “Switched Capacitor Array” Chip

Feb. 26th, 2008Fermilab29 The Domino Principle Shift Register Clock IN Out “Time stretcher” GHz  MHz Waveform stored Inverter “Domino” ring chain ns FADC 33 MHz Keep Domino wave running in a circular fashion and stop by trigger  Domino Ring Sampler (DRS)

Feb. 26th, 2008Fermilab30 Switched Capacitor Array Cons No continuous acquisition No precise timing External (commercial) FADC needed Pros High speed (~5 GHz) high resolution (~12 bit equiv.) High channel density (12 channels on 5x5 mm 2 ) Low power (10 mW / channel) Low cost (< 100$ / channel incl. VME board) tt tt tt tt tt

Feb. 26th, 2008Fermilab31 Folded Layout Linear inverter chain causes non-linearity

Feb. 26th, 2008Fermilab32 “Tail Biting” enable speed

Feb. 26th, 2008Fermilab33 Sample readout 0.2 pF 20 pF DRS1 Tiny signal Temperature Dependence ~kT DRS2 I DRS3

Feb. 26th, 2008Fermilab34 DRS3 Fabricated in 0.25  m 1P5M MMC process (UMC), 5 x 5 mm2, radiation hard 12 ch. each 1024 bins, 6 ch. 2048, …, 1 ch Sampling speed 10 MHz … 5 GHz Readout speed 33 MHz, multiplexed or in parallel 50 prototypes received in July ‘06

Feb. 26th, 2008Fermilab35 VME Board 32 channels input General purpose VPC board built at PSI 40 MHz 12 bit FADC USB adapter board USB adapter board

Feb. 26th, 2008Fermilab36 Bandwidth + Linearity Readout chain shows excellent linearity from 0.1V … 33 MHz readout Analog Bandwidth is currently limited by high resistance of on-chip signal bus, will be increased significantly with DRS4 450 MHz (-3dB) 0.5 mV max.

Feb. 26th, 2008Fermilab37 Signal-to-noise ratio “Fixed pattern” offset error of 5 mV RMS can be reduced to 0.35 mV by offset correction in FPGA SNR: 1 V linear range / 0.35 mV = 69 dB (11.5 bits) “Fixed pattern” offset error of 5 mV RMS can be reduced to 0.35 mV by offset correction in FPGA SNR: 1 V linear range / 0.35 mV = 69 dB (11.5 bits) Offset Correction

Feb. 26th, 2008Fermilab38 12 bit resolution 11.5 bits effective resolution <8 bits effective resolution

Feb. 26th, 2008Fermilab39 Sampling speed PLL Reference Clock (1-4 MHz) V speed ~200 psec Unstabilized jitter: ~70ps / turn Temperature coefficient: 500ps / ºC Unstabilized jitter: ~70ps / turn Temperature coefficient: 500ps / ºC R. Paoletti, N. Turini, R. Pegna, MAGIC collaboration

Feb. 26th, 2008Fermilab40 How far can we go? Maximal sampling speed with current technologies DRS4: 5.5 GHz in favor of linearity and flexibility  m technology maximum: 8 GHz  m technology maximum: 15 GHz Timing in O(10ps) region is tough Sampling has to be close to source (cable effect) TDCs can work in this region (vernier method), but what about discriminator? Probably only possible with analog sampling threshold level first electrons noise timing jitter

Feb. 26th, 2008Fermilab41 Timing Reference signal 20 MHz Reference clock PMT hit Domino stops after trigger latency 8 inputs shift register Reference clock domino wave MUX Calibrate inter-cell  t’s for each chip 200 ps uncertainty using PLL 25 ps uncertainty for timing relative to edge Calibrate inter-cell  t’s for each chip 200 ps uncertainty using PLL 25 ps uncertainty for timing relative to edge

Feb. 26th, 2008Fermilab42 What timing can be obtained? Detailed studies by G. Varner 1) for LAB3 chip Bin-by-bin calibration using a 500 MHz sine wave Accuracy after calibration: 20 ps Detailed studies by G. Varner 1) for LAB3 chip Bin-by-bin calibration using a 500 MHz sine wave Accuracy after calibration: 20 ps 1) G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007) 1ns

Feb. 26th, 2008Fermilab43 On-chip PLL PLL Reference Clock f clk = f samp / 2048 V speed On-chip PLL should show smaller phase jitter If <100ps, no clock calibration required On-chip PLL should show smaller phase jitter If <100ps, no clock calibration required loop filter DRS4 Simulation:

Feb. 26th, 2008Fermilab44 Comparison with other chips MATACQ D. Breton LABRADOR G. Varner DRS3 Bandwidth (-3db) 300 MHz> 1000 MHz450 MHz Sampling frequency 1 or 2 GHz10 MHz … 3.5 GHz10 MHz … 5 GHz Full scale range ±0.5 V+0.4 …2.1 V+0.1 … 1.1V Effective #bits 12 bit10 bit12 bit Sample points 1 x x x 1024 Channel per board 4N/A32 Digitization 5 MHzN/A33 MHz Readout dead time 650  s150  s3  s – 370  s Integral nonlinearity ± 0.1 % ± 0.05% Radiation hard No Yes (chip) Board V1729 (CAEN)-planned (CAEN)

Waveform Analysis What can we learn from acquired waveforms?

Feb. 26th, 2008Fermilab46 On-line waveform display click template fit pedestal histo  848 PMTs “virtual oscilloscope”

Feb. 26th, 2008Fermilab47 QT Algorithm original waveform smoothed and differentiated (Difference Of Samples) Threshold in DOS Region for pedestal evaluation integration area t Inspired by H1 Fast Track Trigger (A. Schnöning, Desy & ETH) Difference of Samples (= 1 st derivation) Hit region defined when DOS is above threshold Integration of original signal in hit region Pedestal evaluated in region before hit Time interpolated using maximum value and two neighbor values in LUT  1ns resolution for 10ns sampling time Inspired by H1 Fast Track Trigger (A. Schnöning, Desy & ETH) Difference of Samples (= 1 st derivation) Hit region defined when DOS is above threshold Integration of original signal in hit region Pedestal evaluated in region before hit Time interpolated using maximum value and two neighbor values in LUT  1ns resolution for 10ns sampling time

Feb. 26th, 2008Fermilab48 Pulse shape discrimination   Leading edge Decay time AC-coupling Reflections

Feb. 26th, 2008Fermilab49  -distribution     = 21 ns   = 34 ns Waveforms can be clearly distinguished   = 21 ns   = 34 ns Waveforms can be clearly distinguished

Feb. 26th, 2008Fermilab50 Coherent noise  i V i (t) All PMTs Pedestal average Charge integration Found some coherent low frequency (~MHz) noise Energy resolution dramatically improved by properly subtracting the sinusoidal background Usage of “dead” channels for baseline estimation Found some coherent low frequency (~MHz) noise Energy resolution dramatically improved by properly subtracting the sinusoidal background Usage of “dead” channels for baseline estimation

Feb. 26th, 2008Fermilab51 Pileup recognition original derivative  t = 15ns E1E2  T 8ns  T 10ns  T 15ns  T 50ns  T 100ns MC simulation Rule of thumb: Pileup can be detected if  T ~ rise-time of signals

Feb. 26th, 2008Fermilab52 Crosstalk elimination Crosstalk removal by subtracting empty channel Hit subtract

Feb. 26th, 2008Fermilab53 Spurious Noise Problem Found “sometimes” a high frequency “ring” on all channels 40 MHz, ~20 mV, 1kHz repetition Finally identified the liquid xenon pump as the source This noise can screw up timing for rare events Without waveform digitizing, this would have been very hard to debug

Feb. 26th, 2008Fermilab54 Template Fit Determine “standard” PMT pulse by averaging over many events  “Template” Find hit in waveform Shift (“TDC”) and scale (“ADC”) template to hit Minimize  2 Compare fit with waveform Repeat if above threshold Store ADC & TDC values  Experiment 500 MHz sampling

Feb. 26th, 2008Fermilab55 High pass filtering original waveform template fit after optimized high pass FIR filter integration area Get rid of baseline (low frequency) noise Improve resolution significantly Get rid of baseline (low frequency) noise Improve resolution significantly

Feb. 26th, 2008Fermilab56 Latch Baseline Subtraction Baseline Subtraction Latch 12 bit 100 MHz Clock    - + <thr  + - Baseline Register Baseline subtracted signal LUT 12x12 Calibrated and linearized signal

Feb. 26th, 2008Fermilab57 Latch Constant Fraction Discr. Latch 12 bit Clock  + + MULT Latch 00 & <0 Delayed signal Inverted signal Sum

Feb. 26th, 2008Fermilab58 Data Reduction Zero suppression: hit if max. value > n x  (baseline) Readout window: start / width in respect to trigger Pile-up flag: Zero-crossings of first derivation Re-binning 4:1, 8:1, 16:1 ADC: Numerical integral of hit over baseline TDC: Only simple threshold (usable to recognize accidentals) and time-over- threshold MEG: Applying to 94% of 100 Hz data Keeping only 6 Hz of waveforms TOT 0.5 ns bins 4 ns bins

Feb. 26th, 2008Fermilab59 Huffman encoding DiffBin. Code DiffBin. Code  Huffman Huffman

Feb. 26th, 2008Fermilab60 Where to perform waveform analysis? Switching from ADC/TDC to ~GHz waveform digitization increases amount of data by ~1000x Many algorithms suitable for on-board (FPGA) processing Charge integration and time estimation (“QT”) Zero-suppression, re-binning, Huffman encoding Basic pile-up recognition (zero-crossings of derivative) Algorithms for embedded CPUs or PC farms Inter-channel cross-talk removal Template fit (floating point) DRS FPGA Front End PC Off-line Analysis

Feb. 26th, 2008Fermilab61 DAQ System Principle Active Splitter Drift Chamber Liquid Xenon CalorimeterTiming Counter Waveform Digitizing Trigger Event number Event type Busy Rack PC optical link (SIS3100) Rack PC Event Builder Switch GBit Ethernet LVDS parallel bus VME

Feb. 26th, 2008Fermilab62 Multi-threading model VME Transfer Thread Calibration Thread Calibration Thread Calibration Thread Calibration Thread Collector Thread VME Round-Robin distribution Network Zero-copy ring buffers

Feb. 26th, 2008Fermilab63 Optimal rate with 4 calibration threads

Feb. 26th, 2008Fermilab64 DAQ System Use waveform digitization (500 MHz/2 GHz) on all channels Waveform pre-analysis directly in online cluster (zero suppression, calibration) using multi-threading MIDAS DAQ Software Data reduction: 900 MB/s  5 MB/s Data amount: 100 TB/year Use waveform digitization (500 MHz/2 GHz) on all channels Waveform pre-analysis directly in online cluster (zero suppression, calibration) using multi-threading MIDAS DAQ Software Data reduction: 900 MB/s  5 MB/s Data amount: 100 TB/year 2000 channels waveform digitizing DAQ cluster

Advanced Topics Reduced dead time, integrated triggering

Feb. 26th, 2008Fermilab66 “Residual charge” problem R “Ghost pulse” 2 GHz “Ghost pulse” 2 GHz After sampling a pulse, some residual charge remains in the capacitors on the next turn and can mimic wrong pulses Solution: Clear before write write clear Implemented in DRS4 Implemented in DRS4

Feb. 26th, 2008Fermilab67 ROI readout mode readout shift register Trigger stop normal trigger stop after latency Delay delayed trigger stop Patent pending! 33 MHz e.g MHz  3 us dead time (2.5 ns / 12 channels)

Feb. 26th, 2008Fermilab68 Daisy-chaining of channels Channel 0 – 1024 cells Channel 1 – 1024 cells Channel 2 – 1024 cells Channel 3 – 1024 cells Channel 4 – 1024 cells Channel 5 – 1024 cells Channel 6 – 1024 cells Channel 7 – 1024 cells Domino Wave Generation DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cells

Feb. 26th, 2008Fermilab69 Interleaved sampling delays (200ps/8 = 25ps) G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007) 5 GSPS * 8 = 40 GSPS

Feb. 26th, 2008Fermilab70 “Almost” Dead time free system CMC1 CMC2 32 channel 16 channel MUX VME board One board is active while other board is read out

Feb. 26th, 2008Fermilab71 DRS4 packaging DRS3 DRS4 9 mm 18 mm 5 mm DRS4 flip-chip

Feb. 26th, 2008Fermilab72 New generation of FADCs 8 simultaneous flash ADCs on one chip Require differential input DRS4 has been redesigned with differential output

Feb. 26th, 2008Fermilab73 Trigger an DAQ on same board Using a multiplexer, input signals can simultaneously digitized at 65 MHz and sampled in the DRS FPGA can make local trigger (or global one) and stop DRS upon a trigger DRS readout (5 GHz samples) though same 8-channel FADCs Multiplexer will be included in DRS4 analog front end DRS FADC 12 bit 65 MHz MUX FPGA trigger LVDS SRAM DRS4 global trigger bus No splitter (signal quality!), no dedicated trigger boards, no dedicated scalers

Feb. 26th, 2008Fermilab74 “Redefinition of DAQ” Because of the high channel density of the DRS system, it becomes affordable to use waveform digitizing in experiments which today use ADC/TCDs ConventionalNew AC couplingBaseline subtraction Const. Fract. DiscriminatorDOS – Zero crossing ADCNumerical Integration TDC Bin interpolation (LUT) Waveform Fitting Scaler (250 MHz)Scaler (50 MHz) OscilloscopeWaveform sampling 400 $ / channel100 $ / channel TDC Disc. ADC Scaler Scope FADC FPGA CPU DRS ~GHz ~100 MHz

Feb. 26th, 2008Fermilab75 Availability DRS4 will become available in larger quantities in summer ’08 Chip can be obtained from PSI on a “non-profit” basis Delivery “as-is” Reference design (schematics) from PSI Costs ~ 10-15$/channel Costs decrease if we find sell more… Full VME board can be purchased from CAEN probably end of ’08 with firmware for peak sensing ADC, QDC, … Struck, others, … ? 32-channel 65 MHz/12bit digitizer “boosted” by DRS4 chip to 5 GHz 32-channel 65 MHz/12bit digitizer “boosted” by DRS4 chip to 5 GHz

Feb. 26th, 2008Fermilab76 Other experiments using DRS MACE Telescope India PET scanners BPM for 8 chn. with PGA Magic Telescope, Canary Islands

Feb. 26th, 2008Fermilab77 Conclusions Switched Capacitor Array techniques has prospects to trigger a quantum step in data acquisition The DRS chip has been designed with maximum flexibility and can therefore be used in many applications Collaboration on a scientific basis is very welcome Datasheets, publications: