ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

Outline Project overview Project-specific success criteria Block diagram Component selection rationale Packaging design Schematic and theory of operation PCB layout Software design/development status Project completion timeline Questions / discussion

Project Overview Modern active loudspeaker system –Intended for consumers –Replaces audio receiver/passive loudspeaker combination Digital manipulation of sound field –User controlled direction –Allows for non-ideal placement in a room

Project-Specific Success Criteria 1. An ability to receive and act upon command from an IR remote. 2. An ability to delay-steer the wave-front of a loudspeaker array (up/down, left/right). 3. An ability to amplitude-shade the wave-front of a loudspeaker array (adjust effective array length). 4. An ability to perform (third-octave) amplitude equalization. 5. An ability to control loudspeaker settings thorough a user interface.

ADSP Analog Switch Parallel Port SPI AD1835A SRAM 4MB Audio Pre-A/D Analog Circuit JTEG Header L R x 2 Audio Inputs Audio Post D/A Analog Circuit 10W Class D Power Amplifier CODEC DSP 2” Speaker 55W Class AB Power Amplifier 8” Subwoofer x 8 FLASH 8MB 25 MHz Oscillator JTEG Port Reset PB Control/User Interface Header DAI Power Supply +12V 8A + A5V 2A Power Regulation +5V +3.3V +1.2V Parallel Port Active Loudspeaker Unit ID Switch Block Diagram

Control Box I/O ATmega16 Touch Button Controller 8 Touch Buttons 8 Program Header Infrared 36kHz Sensor Int. Serial to Video Converter SCI 5.5” LCD TV SPI Control/User Interface Header μCμC Power Regulation +12V +5V +3.3V

Component Selection Rationale Microcontroller –ATmega16 –Freescale 9S12 DSP –ADSP SHARC: Development Environment –TI Aureus™ TMS320DA708 Audio amplifier –TPA3001D1: Class D –TDA2006: Class AB

Packaging Design 40” 9”12” Active Loudspeaker Unit 2” Loudspeaker 8” Subwoofer Array of 8 Loudspeakers Enclosure (MDF) Small Sealed Chamber for each 2” Loudspeaker Sealed Chamber for each 8” Subwoofer Power Supply Subwoofer Amplifier DSP and 8 Channel Amplifier Board Dimensioned DrawingCut-away Drawing Front ViewSide ViewFront ViewSide View

Packaging Design Control/User Interface User Interface Volume + - Input CD TV 7.5” 5.0” 2.0 User Interface Volume + - Input CD TV Capacitance Touch Buttons 5.5” LCD TV Monitor Lexan® Cover Molded Fiberglass Case Standoff Prototype Board for User Interface Touch Button Sensor Video OUT (TV) IR Sensor

Schematic/Theory of Operation DSP/Reset Major Components: –DSP: ADSP –Wireless Transceiver: TRF-2.4G Other Components: –Supply Voltage Monitor: ADM708SARZ –25MHz Oscillator: SGR-8002DC-PCC-ND –SPI Header –JTEG Header

Schematic/Theory of Operation DSP/Reset

Schematic/Theory of Operation Memory Major Components: –SRAM: CYC1049CV33 –Flash: M29W800DB Other Components: –Decoder/Demultiplexer: 74LVC138AD –D-type Latch: 74LVC373APW

Schematic/Theory of Operation Memory

Schematic/Theory of Operation Audio Path Major Components: –Codec: AD1835AASZ –Class-D Audio Power Amplifier: TDA3001D1 Other Components: –Quad SPST Switch: ADG412BR –Low Noise Op-amps: AD8606ARZ –12.288MHz Oscillator: SGR-8002CA-PCC-ND

Schematic/Theory of Operation Audio Input

Schematic/Theory of Operation Analog Audio

Schematic/Theory of Operation Audio Out (1 of 8)

Schematic/Theory of Operation Power Major Components: –Voltage Regulator: ADP3336ARMZ –Step-down Regulator: LTC1877 –Step-down DC-to-DC Controller: ADP1864 –P-channel MOSFET: FDC658P –Power Supply: Commercial Switching Supply Other Components –Through holes

Schematic/Theory of Operation Power A5V ADP1864

Schematic/Theory of Operation Control Box Major Components: –Microcontroller: ATmega16 –Wireless Transceiver: TRF-2.4G –Touch Buttons: E240B –IR Receiver: Radio Shack –Serial to Video Module: ezVID

Schematic/Theory of Operation Control Box

PCB Layout

Power Supply

PCB Layout DSP/Reset/Memory

PCB Layout Audio In

PCB Layout Audio Out

Software Design/Development Status Reset / Power-on Software Initialization (Peripherals, Enable interrupts) Command/Butto n flag set? Reset flag. Update GUI. Transmit data to speakers. Shift in packet contents Process Packet RTI IRQ (Wifi) Yes No

Software Design/Development Status Determine bit received and store it. RTI IRQ interrupt (IR sensor) Set button flag RTI RTI interrupt Button pressed? No Yes Whole command recognized? Set command flag No Yes

Software Design/Development Status Hardware Boot (loads program from Flash) Software Initialization “New data” flag set? Reset “New data” flag. Load new delays, amplitudes, and equalizer coefficients. Load new sample into equalizer buffer. Equalize sample using FIR filter on buffer Put equalized result into delay line buffer Load elements with samples from delay line buffer. RTI Serial port received interrupt Yes No

Software Design/Development Status Begin SPI DMA transfer of received data into memory RTI IRQ interrupt Check received data for lost packet. Send retransmit request via SPI DMA transfer Set “New data” flag RTI SPI transfer complete Lost packet? Yes No

Project Completion Timeline Group Timeline Success Criteria (GTSC) GTSC #1: March 2—Final PCB complete GTSC #2: March 19—Enclosures built GTSC #3: March 30—Components soldered GTSC #4: April 9—Working board GTSC #5: April 27—Project completed

Questions / Discussion