A.Marchioro - CERN/PH1 Accessing 130 nm CMOS Tech for ILC (Public Version) Oct 2006, Munich A. Marchioro CERN, Div. PH 1211 Geneva 23, Switzerland.

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Presentation transcript:

A.Marchioro - CERN/PH1 Accessing 130 nm CMOS Tech for ILC (Public Version) Oct 2006, Munich A. Marchioro CERN, Div. PH 1211 Geneva 23, Switzerland

A.Marchioro - CERN/PH2 Components  Technology  Tools: Design Assistance Package  Services: –Design Services –Prototyping and Production Services

A.Marchioro - CERN/PH3 Technology access  CERN foundry contract –Done! Final prices are fixed, conditions are very interesting and well suited for HEP »Excellent engineering support still in place  Conditions are same or better than those we obtained in 2000 for accessing the ¼ micron generation  Community can globally gain if good coordination will be maintained for the SLHC, ILC and any other future ASIC activity

A.Marchioro - CERN/PH4 Organizational model CERN Foundry Library Vendor MRE INFN Italy IN2P3 France RAL UK MPI Munich… CERN LBL … USA … Suppliers Service Coordination Users

A.Marchioro - CERN/PH5 Technology  For LHC, SLHC, ILC and others –130 nm CMOS, 90 nm later –130 nm BiCMOS »2 flavors available:  Very high Performance  High performance, cost effective »Radiation tolerance to be studied, but large body of work already available.

A.Marchioro - CERN/PH6 MPW Runs  CERN MIC group has organized 16 MPW runs since 2000 in ¼ micron –Each run had up to 20 participants –Easily delivered several hundred chips/run –Smooth transition to production runs –Encourage and support the organization of shared production runs for modest volumes

A.Marchioro - CERN/PH7 130 nm MPW run details  RF process including: –poly and diff resistors –triple well –Low-Vt N and PMOS –Zero-Vt NMOS –e-fuses –Thick (5.2 nm) transistors for 2.5 V  6 metals with LM upper stack, all Cu –Vertical metal to metal cap: 1.3 fF/um 2 –8 metals possible for private runs (+ 64 K$)  Variety of metal capacitors  Bump-bonding if desired (run split possible) –Low cost  Hundreds (or thousands!) of chips from proto run  Preferred chips sizes: multiple of 2x2 mm 2  Cost below MOSIS at about mm 2.

A.Marchioro - CERN/PH8 Technology Design Assistance Package Foundry PDK Cell Library Synopsys & Cadence DSM Tools Custom Design Kit/Wrapper Design Rules Analog Simulation Models Verification Decks Synthesis tools Digital simulation tools Clock Tree Generation Advanced Place & Route Tools Verification Tools ~ 1000 Digital Cells I/O Cells Generators Scripts and Tools to glue all together in one consistent design environment and a strict design flow

A.Marchioro - CERN/PH9 Tools  130 nm “wrapper” available through CERN contract to every HEP Institutes for 2,000 €/year –We expect that “normal” Cadence licenses are available in each Institute –Commercial Digital Library from vendor available for free for download (library is paid by submitted wafers at production time) –A service for advanced P&R and design verification (DRC) can be organized at CERN if enough demand present

A.Marchioro - CERN/PH10 Tools Distribution  The 130 nm Distribution Kit will contain: –Foundry PDK –Digital library –MRE tools –Europractice software will have to be obtained through the normal EU channels  You need to provide to CERN –Copy of NDA with Foundry –Copy of EULA with Library Vendor Do NOT download any private version from the vendors, as they may be out of sync with the CERN version

A.Marchioro - CERN/PH11 Contacts  Organizational issues, contract etc.:  CMOS Technology:  Tools Utilization:  Tools installation issues:  Purchase of MRE Wrapper:

A.Marchioro - CERN/PH12 Future runs  130 nm: –Shared MOSIS run on Nov 25, 2006 –2 MPW runs in 2007 (~ Q2 & Q4) –Tech. details of run from F. Faccio  ¼ micron (as in the past) –1 MPW run in Q2/Q3