Flip Flops 3.1 Latches and Flip-Flops 3 ©Paul Godin Created September 2007 Last Edit Aug 2013.

Slides:



Advertisements
Similar presentations
Tutorial 2 Sequential Logic. Registers A register is basically a D Flip-Flop A D Flip Flop has 3 basic ports. D, Q, and Clock.
Advertisements

Registers and Counters. Register Register is built with gates, but has memory. The only type of flip-flop required in this class – the D flip-flop – Has.
Sequential Digital Circuits Dr. Costas Kyriacou and Dr. Konstantinos Tatas.
CHAPTER 3 Sequential Logic/ Circuits.  Concept of Sequential Logic  Latch and Flip-flops (FFs)  Shift Registers and Application  Counters (Types,
ECE 331 – Digital System Design Latches and Flip-Flops (Lecture #17) The slides included herein were taken from the materials accompanying Fundamentals.
Digital Logic Chapter 5 Presented by Prof Tim Johnson
Sequential Logic Latches and Flip-Flops. Sequential Logic Circuits The output of sequential logic circuits depends on the past history of the state of.
Practice Problems 2 Latch and Flip Flop ©Paul Godin Created September 2007 Last edit Aug 2013.
Sequential Logic Latches & Flip-flops
ReturnNext  Latch : a sequential device that watches all of its inputs continuously and changes its outputs at any time, independent of a clocking signal.
1 Chapter 8 Flip-Flops and Related Devices. 2 Figure 8--1 Two versions of SET-RESET (S-R) latches S-R (Set-Reset) Latch.
EET 1131 Unit 10 Flip-Flops and Registers
1 © 2014 B. Wilkinson Modification date: Dec Sequential Logic Circuits – I Flip-Flops A sequential circuit is a logic components whose outputs.
EKT 124 / 3 DIGITAL ELEKTRONIC 1
Sequential circuit Digital electronics is classified into combinational logic and sequential logic. In combinational circuit outpus depends only on present.
Sequential Logic Flip-Flops and Related Devices Dr. Rebhi S. Baraka Logic Design (CSCI 2301) Department of Computer Science Faculty.
EECC341 - Shaaban #1 Lec # 13 Winter Sequential Logic Circuits Unlike combinational logic circuits, the output of sequential logic circuits.
CSE 140 Lecture 8 Sequential Networks Professor CK Cheng CSE Dept. UC San Diego 1.
ENGIN112 L20: Sequential Circuits: Flip flops October 20, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 20 Sequential Circuits: Flip.
CS 151 Digital Systems Design Lecture 20 Sequential Circuits: Flip flops.
A clocked synchronous state-machine changes state only when a triggering edge or “tick” occurs on the clock signal. ReturnNext  “State-machine”: is a.
Chapter 3: Sequential Logic Circuit EKT 121 / 4 ELEKTRONIK DIGIT 1.
SEQUENTIAL CIRCUITS USING TTL 74XX ICS
Flip Flops. Clock Signal Sequential logic circuits have memory Output is a function of input and present state Sequential circuits are synchronized by.
ETE Digital Electronics Latches and Flip-Flops [Lecture:12] Instructor: Sajib Roy Lecturer, ETE, ULAB.
Objectives: Given input logice levels, state the output of an RS NAND and RS NOR. Given a clock signal, determine the PGT and NGT. Define “Edge Triggered”
Latch Flip flop.
Eng. Mohammed Timraz Electronics & Communication Engineer University of Palestine Faculty of Engineering and Urban planning Software Engineering Department.
Flip-flops. Outline  Edge-Triggered Flip-flops  S-R Flip-flop  D Flip-flop  J-K Flip-flop  T Flip-flop  Asynchronous Inputs.
Introduction to Sequential Logic Design Flip-flops.
Flip Flop
© The McGraw-Hill Companies, Inc McGraw-Hill 1 PRINCIPLES AND APPLICATIONS OF ELECTRICAL ENGINEERING THIRD EDITION G I O R G I O R I Z Z O N I 14.
Flip_Flops  Logic circuits are classified ito two groups  1. The combinational logic circuits,using the basic gates AND,OR and NOT.  2. Sequential.
CHAPTER 3 Sequential Logic/ Circuits.  Concept of Sequential Logic  Latch and Flip-flops (FFs)  Shift Registers and Application  Counters (Types,
Unit 11 Latches and Flip-Flops Fundamentals of Logic Design By Roth and Kinney.
FLIP FLOP By : Pn Siti Nor Diana Ismail CHAPTER 1.
Company LOGO DKT 122/3 DIGITAL SYSTEM 1 WEEK #12 LATCHES & FLIP-FLOPS.
Asynch 1.1 Asynchronous Counters 1 ©Paul Godin Last Edit Sept 2009.
ECA1212 Introduction to Electrical & Electronics Engineering Chapter 9: Digital Electronics – Sequential Logic by Muhazam Mustapha, November 2011.
Introduction to Sequential Logic
Sequential logic circuits
Flip Flop Chapter 15 Subject: Digital System Year: 2009.
Chapter 10 Flip-Flops and Registers 1. Objectives You should be able to: Explain the internal circuit operation of S-R and gated S-R flip-flops. Explain.
Digital Electronics and Computer Interfacing Tim Mewes 3. Digital Electronics.
Synchronous Sequential Logic A digital system has combinational logic as well as sequential logic. The latter includes storage elements. feedback path.
EKT 121 / 4 ELEKTRONIK DIGIT I
Chapter 6 – Digital Electronics – Part 1 1.D (Data) Flip Flops 2.RS (Set-Reset) Flip Flops 3.T Flip Flops 4.JK Flip Flops 5.JKMS Flip Flops Information.
Dept. of Electrical and Computer Eng., NCTU 1 Lab 8. D-type Flip-Flop Presenter: Chun-Hsien Ko Contributors: Chung-Ting Jiang and Lin-Kai Chiu.
Flip Flops 4.1 Latches and Flip-Flops 4 ©Paul Godin Created September 2007 Last edit Sept 2009.
Flip Flops 3.1 Latches and Flip-Flops 3 ©Paul Godin Created September 2007 Last Edit Aug 2013.
7. Latches and Flip-Flops Digital Computer Logic.
Flip-Flop Flip-flops Objectives Upon completion of this chapter, you will be able to :  Construct and analyze the operation of a latch flip-flop made.
UNIT 11 LATCHES AND FLIP-FLOPS Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter in the book includes: Objectives.
DIGITAL LOGIC CIRCUITS 조수경 DIGITAL LOGIC CIRCUITS.
CS1103 Arunima Shukla Asim Marchant Urja Kantharia Harsh kosambia Digital Electronics Mini Project.
LATCHED, FLIP-FLOPS,AND TIMERS
ECE 3130 – Digital Electronics and Design
FIGURE 5.1 Block diagram of sequential circuit
Digital Design Lecture 9
FLIP FLOPS.
Latches and Flip-Flops 2
Elec 2607 Digital Switching Circuits
Lecture No. 24 Sequential Logic.
Latch Practice Problems 1
FLIP-FLOPS.
Latches and Flip-Flops 2
Flip Flops Unit-4.
14 Digital Systems.
Sequential Digital Circuits
FLIPFLOPS.
Presentation transcript:

Flip Flops 3.1 Latches and Flip-Flops 3 ©Paul Godin Created September 2007 Last Edit Aug 2013

Flip Flops 3.2 Edge-Triggered Devices ◊Up to now we have looked at two digital values or states: 1 and 0 ◊There are also two dynamic digital values or states: ◊rising edge (positive edge) ◊falling edge (negative edge) positive edge negative edge 1 0 0

Flip Flops 3.3 Edge-Triggered Devices ◊Inputs to some devices will respond only to a dynamic state. ◊This is known as an edge input or a clock input. ◊The symbol is a triangle at the input. Positive Edge Negative Edge

Flip Flops 3.4 Edge-Triggering Notation ◊Positive Edge: ◊PGT (positive going transition) ◊PT (positive transition) ◊P ◊Negative Edge: ◊NGT (negative going transition) ◊NT (negative transition) ◊N

Flip Flops 3.5 Advantages of Edge-Triggered Devices ◊Edge-Triggered devices are important for many applications, including: ◊Counters ◊Clocks ◊Timers ◊Digital meters ◊Sequential circuits ◊Mathematical operations, … ◊Shift Registers ◊Memory ◊Data communications ◊Logic operations ◊Mathematical operations, …

Flip Flops 3.6 Edge-Triggered D Flip Flop ◊The edge-triggered D-Flip Flop will only read its input when the edge is received. ◊“With an enabling edge, the Q output follows the D input”. D Q Q Clock EnDQQ’Mode 001Reset 110Set 1XQQ’Hold 0XQQ’Hold XQQ’Hold This is one memory cell in computer applications

Flip Flops 3.7 Edge-Triggered SR ◊The edge triggered SR is not very popular. ◊The only difference between the SR Latch and the edge-triggered SR is that it will read its input only when it receives the active edge.

Flip Flops 3.8 Edge-Triggered SR Flip Flop ClkSRQQ’Mode 00QQ’Hold 0101Reset 1010Set 1100Invalid 0XXQQ’Hold 1XXQQ’Hold XXQQ’Hold S R Q Q Clk

Flip Flops 3.9 Edge-Triggered JK Flip Flop ◊The JK Flip Flop is a device that functions like an edge-triggered SR latch. ◊The only exception: toggle state on two active inputs. ◊Toggle means go to the complimentary (opposite) output state. This is a very useful function.

Flip Flops 3.10 Edge-Triggered JK Flip Flop ClkJKQQ’Mode 00QQ’Hold 0101Reset 1010Set 11Q’QToggle 0XXQQ’Hold 1XXQQ’Hold XXQQ’Hold J K Q Q Clk

Flip Flops 3.11 Toggling Toggling has important applications including counters and frequency dividers. A “T” Flip-Flop has a clock input only. The output will toggle on an input edge. T Q Q Clk

Flip Flops 3.12 Exercise 1: Edge-Triggered D Flip Flop Complete the table D Q Q Clock EnDQQ’Mode 0 1 1X 0X X

Flip Flops 3.13 Exercise 2: Edge-Triggered JK Flip Flop ClkJKQQ’Mode XX 1XX XX J K Q Q Clk Complete the table

Flip Flops 3.14 Exercise 3: D Flip Flop timing diagram Complete the timing diagram D Q Q Clk D Q Q Clock

Flip Flops 3.15 Exercise 4: JK Flip Flop timing diagram J K Q Q Clk Complete the timing diagram J K Q Q Clk

Flip Flops 3.16 Exercise 5: JK Flip Flop timing diagram Complete the timing diagram J K Q Q Clk J K Q Q

Flip Flops 3.17 END © GMAIL.COM