1ECE 545 – Introduction to VHDL Project Deliverables

Deliverables 1. Analysis of the Basic Architecture 2. Folded Architecture 3. Unrolled Architecture (waived for most complex hash functions) 4. Embedded-Resource-Based Architecture 2

For Folded/Unrolled/Embedded-Resource-Based 1. General and Detailed block diagrams of the Datapath with names of intermediate signals matching VHDL code [electronic version in Xfig/Visio and PDF] 2. Interface with the division into the Datapath and the Controller [electronic version in Xfig/Visio/PPT, and PDF] 3. ASM charts of the Controller, and a block diagram of connections among FSMs (if more than one used) [scanned handwritten version OK, electronic version in Visio a bonus] 4. RTL VHDL code of the Datapath, the Controller, and the Top-Level Circuit 5. Updated timing analysis (execution time and throughput); formulas for timing confirmed through simulation 3

Deliverables (2) 6. Report on verification − result of verification Functional simulation Post-synthesis simulation (Virtex 5, Spartan 3 or Virtex 4) Timing simulation (Virtex 5, Spartan 3 or Virtex 4) − if result negative, please describe incorrect behavior and possible sources of errors 4

Deliverables (3) 7. Report on benchmarking using ATHENa – Xilinx Spartan 3, Virtex 5, Cyclone II, and Stratix III required – Spartan 6, Virtex 6, Cyclone IV, and Stratix IV (bonus). – Optimization strategies used to obtain best results single_run (minimum), other ATHENa optimizations (bonus) – Graphs and charts – Observations and conclusions 5

6 CubeHash x1 – basic iterative /2(h) – folded horizontally by a factor of 2 x2 – two times unrolled

Bonus Deliverables (4) 8. Bugs and suspicious behavior of ATHENa. Feedback on the difficulty of use and desired features. 9. Generating results for the ATHENa database 7

For Basic Architecture 1. Report on verification − result of verification Functional simulation Post-synthesis simulation (Virtex 5, Spartan 3 or Virtex 4) Timing simulation (Virtex 5, Spartan 3 or Virtex 4) − if result negative, please describe incorrect behavior and possible sources of errors 8

Deliverables (2) 2. Report on benchmarking using ATHENa – Xilinx Spartan 3, Virtex 5, Cyclone II, and Stratix III required – Spartan 6, Virtex 6, Cyclone IV, and Stratix IV (bonus). – Optimization strategies used to obtain best results single_run (minimum), other ATHENa optimizations (bonus) – Observations and conclusions 9

Bonus Deliverables (3) 3. Bugs and inefficiencies found in the – Block diagrams – ASM charts – Source codes – Discrepancies between source codes and Block diagrams and ASM charts – Testbench – Padding script – Documentation 4. Comments and meaningful names 10