Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory21 October 2002 CMS Tracker FED Back End FPGA Frame_Sync_out0 Frame_Sync_In0 Readout_Sync_out0 Readout_Sync_In0 Monitor_out0 Monitor_In0 Data_stream0 Clock40 Reset FE0 Frame_Sync_out7 Frame_Sync_In7 Readout_Sync_out7 Readout_Sync_In7 Monitor_Sync_out7 Monitor_Sync_In7 Data_stream7 FE7 SLINK64 TTS VME Internal ADDR/CNTRL DATA IN DATA OUT QDR SSRAM TTCrx BSCAN SLINK Temp Sense diode Bank Voltages Core Voltage Bank DCI Resistors 12 x2 QDR Common Address Config_In0 Config_out0 Full flags3 Temp Flags2 LM Clock LVDS ef, pf & ff ‘I2C’ Single ended DCI LVDS pair option J0 J2 ~64K 7 pairs pairs

Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory21 October 2002 CMS Tracker FED Back End FPGA Frame_Syncs Readout_Syncs Spare x8 TTC Rx TTS 9 ‘VME’ DECODE CONTROL & MONITOR Data_stream 0 Data_stream Data In 20 Address 18 Data Out 8 SLINK/Channel Link 64 R/W Address Generator Data 80 MHz MHz 40 Mhz Clock40 in Reset DCMs x4 x1 x2 QDR SSRAM x2/x4 burst 320 MHz 80/160 MHz 640 MHz LVDS 8x Lengths, Pointers Header FF/PF Flags Control In 8 DDR Out Control DDR Load_monitor x8 Channel Link 3 3 8x DataControl Fill/run/freeze FF, PF, busy Reset 8 Clock40 out

Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory21 October 2002 Back End Control Block Frame Sync Interface VME Interface Readout Sync Interface Load/Monitor Interface Flow Control Interface Address Data Control VME Control FS in 0..7 RS in 0..7 Load 0..7 Monitor 0..7 FE FPGA FF/PF 0..1 TTS 0..X SLINK CTRL 0..X FS out 0..7 RS out 0..7 Reset Header Generation Header Header Data Address Generator Data Address Generator Control Data tap 0..X SLINK-VME SLINK Data TTC Interface TTC 0..9 Event Scalers

Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory21 October 2002 Frame Sync Serial Detect Compare FS in 0..7 FIFO 1K CTRL BUS HEADER BUS fs_strobe, status= good, some header errors, arrival time error, fatal error fs_fifo_empty, fs_fifo_full, fifo_data=median header+status DPM 1K VME BUS 8x Serial Data, markers & control data circular buffer reset, freeze

Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory21 October 2002 Readout Sync Serial Detect RS in 0..7 FIFO 8K CTRL BUS HEADER BUS rs_strobe, status= good, arrival time error, fatal error copy_fifo_empty, copy_fifo_full, fifo_data= sub_lengths DPM 1K VME BUS 8x Serial Data, markers & control data circular buffer reset, freeze,readout_next RS out 0..7 FIFO 8K fifo_data= 8x sub_lengths FIFO 8K fifo_data= 8x pointer_offsets FIFO 1K Address Gen Total_length_fifo_empty, total_length_fifo_full, fifo_data= total length

Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory21 October 2002 Load/Monitor Serial I/O Engine Config in 0..7 DPM 1K ‘VME’ BUS Output Config out 0..7 DPM 1K Serial I/O Engine Monitor in 0..7 DPM 1K ‘VME’ BUS Monitor out 0..7 DPM 1K Input Output Input

Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory21 October 2002 SLINK-VME VME-SLINK Readout ‘VME’ BUS QDR/SLINK Interface CTRL BUS QDR Event Data moved in blocks into DPM Burst transfer over VME Wait on software handshake before continuing Double buffered DPM 1K FIFO 1K

Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory21 October 2002 TTC Interface TTC Interface TTC 0..9 FIFO 1K FIFO 1K DPM 1K Header VME CTRL BUS ttc_strobe reset, freeze Bx,Ex Em Hdr

Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory21 October 2002 Flow Control core FE FPGA PF TTS BUSY Addr GEN FF FE FPGA FF Internal FIFO FF Internal FIFO PF Internal Freeze Latch Fill Flow Control Internal FIFO EF SLINK CTRL Busy Empty Flow Control Addr GEN EF Addr GEN Controls RS Controls Internal Freeze Addr Gen FIFO PF Addr Gen FIFO FF Simplest flow control; Halt on any buffer full Busy on any buffer partially full Simplest flow control; Halt on any buffer full Busy on any buffer partially full Addr GEN Busy VME soft reset Circular Buffers VME Fill event Readout event Diagnostic Event Logger Control Registers Time stamped

Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory21 October 2002 HeaderData ADC Output Frame Sync Status Message CMS Tracker FED System Timing Handshake Message Frame Sync In Readout Sync In Processed Message Readout Message #2234 #2233 #2220#2221 Data Burst #2220#2221 Data Data Burst #2219 Frame Sync Out Median header+ Accept/abort Length Readout Sync Out Next/delete NB Frame Sync In - Abort/Accept not used, auto accepts. Readout Sync In - delete not used.

Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory21 October 2002 CMS Tracker FED Back End FPGA Read Ptr Write Ptr 0 Write Ptr 1 Write Ptr 2 Write Ptr 7 Read Ptr Write Ptr 0 Write Ptr 1 Write Ptr 2 Write Ptr 7 Event N-1 Event N+1 Event N-1 Read Ptr Write Ptr 0 Write Ptr 1 Write Ptr 2 Write Ptr 7 Event N-1 Event N+1 #00000 #FFFFF Event N FE 0 FE 1 FE 7 T0T1T2 Header Ptr

Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory21 October 2002 CMS Tracker FED - Back End FPGA Floorplan FE_FPGA_Inputs SLINK QDR XC2V1500FG I/O XC2V1000FG I/O XC2V2000FG I/O XC2V3000FG I/O Same frame 456 & 676 ? Clocks DiePackage VME