Chapter 18 Paging Chien-Chung Shen CIS, UD

Introduction Our goal: to virtualize memory Segmentation (generalization of dynamic relocation) can do it, but has issues –managing free space with external fragmentation Fixed vs. variable sized units Paging: virtualize memory without segmentation e.g., 64-byte address space with 4 pages

Paging Page frame in physical memory Advantages: –flexibility – works, no matter how process uses its address space –simplicity of free space management How to record where each virtual page is placed in physical memory? –per-process page table

Address Translation Split address into virtual page # (VPN) and offset –64-byte address space –page size = 16 bytes –VA 21 –VPN indexes page table to get physical frame # (PFN) –offset stays the same

Where Are Page Tables Stored 32-bit address space with 4KB pages –20-bit VPN and 12-bit offset –4 bytes per page table entry (PTE): 4MB = 4×2 20 –page tables are stored in “kernel” memory

Structure of Page Table Linear page table (an array) –OS indexes the array by VPN to get PFN Bits associated with each PTE –valid –protection: for R, W, X –present –dirty –reference (access)

Paging Is Too Slow movl 21, %eax To fetch data in virtual address 21, translate 21 into physical address (117) –fetch PTE (in memory) to perform translate –where is the page table for the running process? page-table base register: physical address of the starting location of the page table VPN = (VirtualAddress & VPN_MASK) >> SHIFT PTEAddr = PageTableBaseRegister + (VPN * sizeof(PTE)) VPN_MAST = and SHIFT = 4 hardware fetches PTE from memory to get PFN and concatenate it with offset from the virtual address to form the desired physical address offset = VirtualAddress & OFFSET_MASK PhysAddr = (PFN << SHIFT) | offset –hardware fetch the desired data from memory and put it into eax

Summary // Extract the VPN from the virtual address VPN = (VirtualAddress & VPN_MASK) >> SHIFT // Form the address of the page-table entry (PTE) PTEAddr = PTBR + (VPN * sizeof(PTE)) // Fetch the PTE PTE = AccessMemory(PTEAddr) // Check if process can access the page if (PTE.Valid == False) RaiseException(SEGMENTATION_FAULT) else if (CanAccess(PTE.ProtectBits) == False) RaiseException(PROTECTION_FAULT) else // Access is OK: form physical address and fetch it offset = VirtualAddress & OFFSET_MASK PhysAddr = (PTE.PFN << PFN_SHIFT) | offset Register = AccessMemory(PhysAddr) For every memory reference (whether an instruction fetch or an explicit load or store), paging requires to perform one extra memory reference in order to first fetch the translation from the page table

Memory Trace int array[1000]; for (i = 0; i < 1000; i++) array[i] = 0; $ objdump –d a.out 0x1024 movl $0x0,(%edi,%eax,4) // move 0 into VA of array [edi]+4*[eax] 0x1028 incl %eax 0x102c cmpl $0x03e8,%eax // 0x03e8 = x1030 jne 0x1024 Virtual address space of size 64 KB and page size 1 KB Each instruction fetch generates 2 memory references: one to page table to find the physical frame that the instruction resides within, and one to instruction itself to fetch it to the CPU for processing movl adds another page table access and then the array access itself

Memory Trace of 1 st 5 Loops Page table: PA 1024 Code: VA Array: VA to (VPN 39-42) Page table: VPN 1 -> PFN 4 VPN 39 -> PFN 7 VPN 40 -> PFN 8 VPN 41 -> PFN 9 VPN 42 -> PFN 10

Summary Advantages (over segmentation) –no external fragmentation (with fixed sigze pages) –flexible to enable the sparse use of virtual address spaces Disadvantages –slow (extra memory accesses to access the page table) –memory waste (with memory filled with page tables instead of application data)