CS/CoE 536 : Lockwood 1 CS/CoE 536 Reconfigurable System On Chip Design Lecture 4 : Demonstration of Machine Problem 1 : CAM-based Firewall Washington University Fall Chris Neely, Chris Zuver Copyright 2002

CS/CoE 536 : Lockwood 2 MP1 Packet Classification Hardware CAM_MASK_2 CAM_VALUE_ Src IP Dest IP Src Port Dest Port CAM_MASK_1 CAM_VALUE_ Drop match <= ‘1’ when (input = 0xFFFFFFFFFFFFFFFFFFFFFFFFFF”) else ‘0’; Proto

CS/CoE 536 : Lockwood 3 Protocol Headers Cell Header IP Header UDP IP Header Payload PAD AAL5 Trailer AAL5 Frame Checksum AAL5 Frame LenCPS-UU & CPI AAL5 Pad

CS/CoE 536 : Lockwood 4 Protocol Wrappers Timing Diagram DataEn SOF EOF Data SOC Data SOD AAIIIIIUUDDDDDDDDDDDDAA--PPPFF-- A-IIIIIUDDDDD----DDDDDDDFF----- A - I U U FP DATM HeaderIP Header Don't careFrame TrailerPadding Payload Data UDP Header CLK Cell Level Frame Level IP Level Only use these signals to process UDP/IP packets UDP payload starts 2 cycles after SOD signal. UDP payload ends with EOF signal. This cycle is optional. It does not appear in simulation Data Enabled during frame trailer

CS/CoE 536 : Lockwood 5 State Transitions for Processing Packet States correspond to order of data in the packet header. State transition are based on data_en=‘1’ idle ver flags ttl srcip_ttl_1 dstip_ttl_2 ports_ttl_3 checksum_ttl_4 xmit GIVEN FSM

CS/CoE 536 : Lockwood 6 CAM Update Datagram Special UDP/IP Datagram updates values of CAM Entries –Allows software- controlled update of CAM registers –Fields alocated for: CAM_VALUE_1 CAM_MASK_1 CAM_VALUE_2 CAM_MASK_2 ATM Header Packet Len Source IP address ( 0xC0A81E0D ) (Reserved) CAM_1_SRC_IP CAM_MASK_1 … (if necessary) ToSHLVer FragmentIP ID Src Port Dest Port ( 0x0320 ) LengthChecksum # CAMs AAL5 Pad CPS-UU & CPI AAL5 Frame Checksum Frame Len CAM_1_DEST_IP CAM_1_PORTS CAM_1_ PROTO (PAD) CAM_2_SRC_IP CAM_MASK_2 CAM_2_DEST_IP CAM_2_PORTS CAM_2_ PROTO (PAD) CAM_VALUE_1 CAM_MASK_1 CAM_VALUE_2 CAM_MASK_2 ChecksumProtoTTL

CS/CoE 536 : Lockwood 7 State Transitions for updating CAMs idle ver flags ttl srcip_ttl_1 dstip_ttl_2 ports_ttl_3 checksum_ttl_4 xmit GIVEN FSM control_ports_ttl_3 Data_flop = x”C0A80101” Data_flop(15..0) /= x”0320” control_checksum_ttl_4 control_ports_ttl3 control_cam_header control_cam1_src_entry control_cam1_dst_entry control_cam1_ports_entry control_cam1_proto_entry control_cam1_src_mask control_cam1_dst_mask control_cam1_ports_mask control_cam1_proto_mask control_cam2_src_entry control_cam2_dst_entry control_cam2_ports_entry control_cam2_proto_entry control_cam2_src_mask control_cam2_dst_mask control_cam2_ports_mask control_cam2_proto_mask eof_flop=‘1’ and den_flop=‘1’ eof_flop=‘0’ and den_flop=‘1’ State transition are based on data_en=‘1

CS/CoE 536 : Lockwood 8 FPX Hardware Design Flow Place and Route with constraints (Xilinx) Synthesize Logic to Xilinx gate technology (Synplicity) Verify Functionality (vsim) Test Module with actual traffic input Constrain Placement to FPX RAD Upload bitfile To FPX for testing Verify Post Place & Route Timing (ModelSim) Generate bitstream (Xilinx) Verify that that resulting packets have correct TTL Compile circuit (vcom)

CS/CoE 536 : Lockwood 9 Accessing FPGA Design Tools in Sever 201 Opening Cygwin, ModelSim, and Synplicity –Start Menu --> Engineering --> FPGA Tools

CS/CoE 536 : Lockwood 10 Downloading and extracting MP1 files Download the MP1 tar file from the website. Save the file under your CEC home directory (e.g. H:\cs536\mp1) Extract the files from Cygwin: –tar xvfz FireWall.tar.gz

CS/CoE 536 : Lockwood 11 VHDL EDITORS EMACS –emacs /vhdl/wrapper_app.vhd & –Good for beginners VI –vi /vhdl/wrapper_app.vhd ModelSim –Click open.. Browse to /vhdl/wrapper_app.vhd Synplicity –Open wrapper_app.vhd OTHER ………..

CS/CoE 536 : Lockwood 12 Compiling the design Compiling the tools –cd H :\cs536\mp1\FireWall –make compile Simulating the Design –make sim (It may take a couple minutes to load the simulation.)

CS/CoE 536 : Lockwood 13 ModelSim Simulation ModelSim Workspace Run simulation Open windows Select entity Select signals Force values View simulation waveforms ModelSim’s Status (ex. Loading…)

CS/CoE 536 : Lockwood 14 ModelSim Simulation [continued] Zooming in on waveforms Incoming packet Outgoing packet Custom Zoom Zoom Full

CS/CoE 536 : Lockwood 15 ModelSim Simulation [continued] TTL Src IP Dest IP TTL ≠ 0 Src IP Transmitted Packet

CS/CoE 536 : Lockwood 16 Editing wrapper_app.vhd From cygwin –Emacs /sim/wrapper_app.vhd From Emacs –Scroll to the Signal Process Line 248 –Change the null assignment for state dstip_ttl_2 to assign data_buf2(31 downto 24) to zero. This sets TTL to zero. –Exact code is shown in diagram.

CS/CoE 536 : Lockwood 17 ModelSim Simulation [continued] TTL Src IP Dest IP TTL = 0 Src IP Dropped Packet

CS/CoE 536 : Lockwood 18 Testbench Data Sample format of input data file (/sim/INPUT_CELLS.DAT) Compared to output data file (/sim/LC_CELLSOUT.DAT) Transmitted Packet Dropped Packet

CS/CoE 536 : Lockwood 19 Synthesizing the Design (Synplicity) Open the project file: /syn/wrapper_app.prj Listing of the synthesizable vhdl files in the design. The files are listed in bottom-up order Wrapper_app.ssr Error/Warnings log with estimated timing information Target FPGA Xilinx Virtex-E XCV2000E -7 FG680

CS/CoE 536 : Lockwood 20 Synthesizing the Design [continued] Synplicity from the Cygwin console –make syn Quick method Poor feedback: must open wrapper_app.srr to view details.

CS/CoE 536 : Lockwood 21 Backend Tools : Generating the Bitstream Xilinx Tools –make build Build Script (/syn/rad-xcv2000e/build) #!/bin/bash part=xcv2000e-7-fg680 #defines the target device design=wrapper_app #defines the design name used in Synplicity ngdbuild -p ${part} ${design} -uc fpx.ucf #Parses netlist into logical description map -p ${part} -o top.ncd ${design}.ngd ${design}.pcf #Maps description into components par -w -ol 2 top.ncd ${design}.ncd ${design}.pcf #Connects and positions components trce ${design}.ncd ${design}.pcf -e 2 -o ${design}.twr #Generates a timing report bitgen ${design}.ncd -b -l -w -f bitgen.ut #Creates the bitstream to program the FPGA More information about these tools is available in the CEC under: P:\Xilinx42\doc\usenglish\docs\dev

CS/CoE 536 : Lockwood 22 Testing the design on the FPX NCHARGE website for automated testing: Username –Cs536 Password –soc_firewall

CS/CoE 536 : Lockwood 23 Testing the design on the FPX Click TEST BIT FILE Enter Class ID (5 digit) Enter MP1 Click Create Entry Locate empty file in list of files. Click Upload next to file Click Browse and select /syn/rad-scv2000e/wrapper_app.bit

CS/CoE 536 : Lockwood 24 Verifying the Results After uploading your bitfile the website will automatically load your design into an FPX, create traffic, send the traffic, and return a results file showing the tests. To view results (this may take several minutes to appear after uploading) click on the results link under “TEST BIT FILE.”

CS/CoE 536 : Lockwood 25 Creating the waveforms Generating postscript files from ModelSim 1.Adjust ModelSim wave window such that all important information needed to verify your results are visible (a.k.a zoom in enough to see data values, etc) 2.From the file menu select Print Postscript…\ 3.Specify the filename and select “current view” for both signals and time range.

CS/CoE 536 : Lockwood 26 Creating the waveforms (cont.) Converting postscript files to PDF format from Cygwin. –ps2pdf input.ps > output.pdf If your.ps file will not display using Ghostview then try this command to fix the errors. –ps2ps input.ps output.ps

CS/CoE 536 : Lockwood 27 Uploading your solutions Open the page –