1 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) CPRE 583 Reconfigurable Computing Lecture 9: Wed 9/21/2011 (Reconfigurable Computing Architectures) Instructor: Dr. Phillip Jones Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA

2 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) MP1: Due Friday (9/23), and MP2 will be released on Friday as well. Mini literary survey assigned –PowerPoint tree due: Fri 9/23 by class, so try to have to me by 9/22 night. My current plan is to summarize some of the classes findings during class. –Final 5-10 page write up on your tree due: Fri 9/30 midnight. Announcements/Reminders

3 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Start with searching for papers from on IEEE Xplorer: –Advanced Search (Full Text & Meta data) Find popular cross references for each area For each area try to identify 1 good survey papers For each area –Identify 2-3 core Problems/issues –For each problem identify 2-3 Approaches for addressing –For each approach identify 1-2 papers that Implement the approach. Literary Survey

4 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Literary Survey: Example Structure Network Intrusion Detection P1 P2P3 A1A2A3A1A2A1A2 I1 I2I1 I2I page write up on your survey tree

5 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Network Intrusion Detection Systems detection accuracy signatures The Study on Network Intrusion Detection System of Snort heuristics An FPGA-Based Network Intrusion Detection Architecture adaptability to new threats neural networks Network Intrusion Detection Method Based on Radial Basic Function Neural Network principal component analysis An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection System support vector machine Network Intrusion Detection Based on Support Vector Machine Network Intrusion Detection Method Based on Agent and SVM Fall 2010 Student Example

6 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Chapter 2 (Reconfigurable Architectures) Overview

7 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Common Questions

8 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Common Questions

9 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Common Questions

10 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Basic trade-offs associated with different aspects of a Reconfigurable Architecture. (Chapter 2) What you should learn

11 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Reconfigurable Architectures Main Idea Chapter 2’s author wants to convey –Applications often have one or more small computationally intense regions of code (kernels) –Can these kernels be sped up using dedicated hardware? –Different kernels have different needs. How does a kernels requirements guide design decisions when implementing a Reconfigurable Architecture?

12 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Reconfigurable Architectures Forces that drive a Reconfigurable Architecture –Price Mass production 100K to millions Experimental 1 to 10’s –Granularity of reconfiguration Fine grain Course Grain –Degree of system integration/coupling Tightly Loosely All are a function of the application that will run on the Architecture

13 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Example Points in (Price,Granularity,Coupling) Space Price $100’s $1M’s Granularity Coarse Fine Coupling Loose Tight Intel / AMD Int float RFU Processor PC ML507 Ethernet Decode Exec Store

14 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) What’s the point of a Reconfigurable Architecture Performance metrics –Computational Throughput Latency –Power Total power dissipation Thermal –Reliability Recovery from faults Increase application performance!

15 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Typical Approach for Increasing Performance Application/algorithm implemented in software –Often easier to write an application in software Profile application (e.g. gprof) –Determine where the application is spending its time Identify kernels of interest –e.g. application spends 90% of its time in function matrix_multiply() Design custom hardware/instruction to accelerate kernel(s) –Analysis to kernel to determine how to extract fine/coarse grain parallelism (does any parallelism even exist?) Amdahl’s Law!

16 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Amdahl’s Law: Example Application My_app –Running time: 100 seconds –Spends 90 seconds in matrix_mul() What is the maximum possible speed up of My_app if I place matrix_mul() in hardware? What if the original My_app spends 99 seconds in matrx_mul()? 10 seconds = 10x faster 1 seconds = 100x faster Good FPGA paper that illustrates increasing an algorithm’s performance with Hardware “NOVEL FPGA BASED HAAR CLASSIFIER FACE DETECTION ALGORITHM ACCELERATION”, FPL

17 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity

18 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: Coarse Grain rDPA: reconfigurable Data Path Array Function Units with programmable interconnects ALU Example

19 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: Coarse Grain rDPA: reconfigurable Data Path Array Function Units with programmable interconnects ALU Example

20 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: Coarse Grain rDPA: reconfigurable Data Path Array Function Units with programmable interconnects ALU Example

21 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: Fine Grain FPGA: Field Programmable Gate Array Sea of general purpose logic gates CLB Configurable Logic Block

22 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: Fine Grain FPGA: Field Programmable Gate Array Sea of general purpose logic gates CLB Configurable Logic Block

23 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: Fine Grain FPGA: Field Programmable Gate Array Sea of general purpose logic gates CLB Configurable Logic Block

24 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: Trade-offs Trade-offs associated with LUT size Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits) 1024-bits 2-LUT 10-LUT Microprocessor

25 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: Trade-offs Trade-offs associated with LUT size Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits) 1024-bits 2-LUT 10-LUT Microprocessor A B op 3

26 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: Trade-offs Trade-offs associated with LUT size Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits) 1024-bits 2-LUT 10-LUT Microprocessor A B op A B A B 3

27 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: Trade-offs Trade-offs associated with LUT size Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits) 1024-bits 2-LUT 10-LUT Microprocessor A B op A B A B

28 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: Trade-offs Trade-offs associated with LUT size Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits) 1024-bits 2-LUT 10-LUT Microprocessor A B op 3

29 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: Trade-offs Trade-offs associated with LUT size Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits) 1024-bits 2-LUT 10-LUT Bit logic and constants

30 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: Trade-offs Trade-offs associated with LUT size Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits) 1024-bits 2-LUT 10-LUT Bit logic and constants (A and “1100”) or (B or “1000”)

31 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: Trade-offs Trade-offs associated with LUT size Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits) 1024-bits 2-LUT 10-LUT Bit logic and constants (A and “1100”) or (B or “1000”) A B

32 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: Trade-offs Trade-offs associated with LUT size Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits) 1024-bits 2-LUT 10-LUT Bit logic and constants (A and “1100”) or (B or “1000”) A AND OR 1 0 B 4 4 It’s much worse, each 10-LUT only has one output Area that was required using 2-LUTS

33 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: Example Architectures Fine grain: GARP Course grain: PipeRench

34 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: GARP CPU RFU Garp chip Memory I-cache D-cache Config cache

35 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: GARP CPU RFU Garp chip Memory I-cache D-cache Config cache RFU control (1) Execution (16, 2-bit) N PE (Processing Element)

36 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: GARP CPU RFU Garp chip Memory I-cache D-cache Config cache RFU control (1) Execution (16, 2-bit) N PE (Processing Element) Example computations in one cycle A<<10 | (b&c) (A-2*b+c)

37 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: GARP CPU RFU Garp chip Memory I-cache D-cache Config cache Impact of configuration size 1 GHz bus frequency 128-bit memory bus 512Kbits of configuration size On a RFU context switch how long to load a new full configuration? 4 microseconds An estimate of amount of time for the CPU perform a context switch is ~5 microseconds ~2x increase context switch latency!!

38 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: GARP CPU RFU Garp chip Memory I-cache D-cache Config cache RFU control (1) Execution (16, 2-bit) N PE (Processing Element) “The Garp Architecture and C Compiler”

39 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: PipeRench Coarse granularity Higher (higher) level programming Reference papers PipeRench: A Coprocessor for Streaming Multimedia Acceleration (ISCA 1999): PipeRench Implementation of the Instruction Path Coprocessor (Micro 2000): pdf pdf

40 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: PipeRench Interconnect 8-bit ALU Reg file PE 8-bit ALU Reg file PE 8-bit ALU Reg file PE Interconnect 8-bit ALU Reg file PE 8-bit ALU Reg file PE 8-bit ALU Reg file PE 8-bit ALU Reg file PE 8-bit ALU Reg file PE 8-bit ALU Reg file PE Global bus

41 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: PipeRench PE Cycle Pipeline stage

42 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: PipeRench PE 0 Cycle Pipeline stage

43 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: PipeRench PE 0 Cycle Pipeline stage

44 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: PipeRench PE 0 Cycle Pipeline stage

45 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: PipeRench PE 0 Cycle Pipeline stage

46 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: PipeRench PE 0 Cycle Pipeline stage

47 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: PipeRench PE 0 Cycle Pipeline stage

48 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: PipeRench PE 0 Cycle Pipeline stage Cycle Pipeline stage

49 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: PipeRench PE 0 Cycle Pipeline stage Cycle Pipeline stage

50 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: PipeRench PE 0 Cycle Pipeline stage Cycle Pipeline stage

51 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: PipeRench PE 0 Cycle Pipeline stage Cycle Pipeline stage

52 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: PipeRench PE 0 Cycle Pipeline stage Cycle Pipeline stage

53 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: PipeRench PE 0 Cycle Pipeline stage Cycle Pipeline stage

54 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: PipeRench PE 0 Cycle Pipeline stage Cycle Pipeline stage

55 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Degree of Integration/Coupling Independent Reconfigurable Coprocessor –Reconfigurable Fabric does not have direct communication with the CPU Processor + Reconfigurable Processing Fabric –Loosely coupled on the same chip –Tightly coupled on the same chip

56 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Degree of Integration/Coupling Main Memory CPU Fetch Decode Execute Memory Write Back L1 Cache L2 Cache Memory Controller DMA Controller I/O Controller USB PCI PCI-ExpressSATA Hard Drive NIC ALU FPU

57 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Degree of Integration/Coupling Main Memory CPU Fetch Decode Execute Memory Write Back L1 Cache L2 Cache Memory Controller DMA Controller I/O Controller USB PCI PCI-ExpressSATA Hard Drive NIC ALU FPU RPF

58 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Degree of Integration/Coupling Main Memory CPU Fetch Decode Execute Memory Write Back L1 Cache L2 Cache Memory Controller DMA Controller I/O Controller USB PCI PCI-ExpressSATA Hard Drive NIC ALU FPU RPF

59 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Degree of Integration/Coupling Main Memory CPU Fetch Decode Execute Memory Write Back L1 Cache L2 Cache Memory Controller DMA Controller I/O Controller USB PCI PCI-ExpressSATA Hard Drive NIC ALU FPU RPF Config I/F

60 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Degree of Integration/Coupling Main Memory CPU Fetch Decode Execute Memory Write Back L1 Cache L2 Cache Memory Controller DMA Controller I/O Controller USB PCI PCI-ExpressSATA Hard Drive NIC ALU FPU RPF Config I/F

61 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Degree of Integration/Coupling Main Memory CPU Fetch Decode Execute Memory Write Back L1 Cache L2 Cache Memory Controller DMA Controller I/O Controller USB PCI PCI-ExpressSATA Hard Drive NIC ALU FPU RPF I/O Config I/F

62 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Degree of Integration/Coupling Main Memory CPU Fetch Decode Execute Memory Write Back L1 Cache L2 Cache Memory Controller DMA Controller I/O Controller USB PCI PCI-ExpressSATA Hard Drive NIC ALU FPU RFU

63 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames)

64 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Next Class Reconfiguration Management –Chapter 4

65 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Questions/Comments/Concerns Write down –Main point of lecture –One thing that’s still not quite clear –If everything is clear, then give an example of how to apply something from lecture OR

66 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Lecture notes

67 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: PipeRench Scheduling virtual stage on to physical Partial/Dynamically reconfig (each cycle)

68 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Granularity: GARP Impact of configuration size on performance Context switching Garp feature Dynamic reconfigurable Store multiple configurations in an on chip cache (4) One configuration at a time Example app mapping to GARP (loop) Amdahl's Law The Garp Architecture and C Compiler

69 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Overview Dimensions –Price –Granularity –Coupling –To optimize App Performance (compute (throughput, latency), Power, reliability) RPF to efficiently implement VICs –Main picture authors' wants to convey What’s the point or having a Reconfigure arch –Example (Increase App performance) App -> SW/CPU Profile ID kernels of intense compute Design custom hardware/instruction (Amdels law) –Intel FPL paper, great example for reading by Friday

70 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Reconfigurable Architectures RPF -> VIC (short slide)