L16 – VHDL for State Machines with binary encoding

VHDL – binary encoded states  Another example Counter – enumeration states Binary encoded states Gray Code Controlled counters  Ref: text Unit 10, 17, 20 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU2

Counter example  Specification – Write a synthesizable VHDL description of a 3-bit counter that counts from 0 to 7 in binary, i.e., 000, 001, 010, …, 110, 111.  A 3-bit counter has 8 states, so,s1, …, s8.  The state occur sequentially without control. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU3

Start the HDL  This is a problem that one should be able to do without a state diagram to start.  The entity ENTITY cnt3bit IS PORT(clk : IN bit; cnt : OUT bit_vector(2 downto 0)); END cnt3bit; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU4

The ARCHITECTURE ARCHITECTURE one OF cnt3bit IS TYPE state_type IS (s0,s1,s2,s3,s4,s5,s6,s7); SIGNAL state,next_state : state_type; BEGIN --F/F process PROCESS BEGIN WAIT UNTIL clk='1' AND clk'event; state <= next_state; END PROCESS; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU5

The next state process --next_state process PROCESS (state) BEGIN CASE state IS WHEN s0 => next_state <= s1; WHEN s1 => next_state <= s2; WHEN s2 => next_state <= s3; WHEN s3 => next_state <= s4; WHEN s4 => next_state <= s5; WHEN s5 => next_state <= s6; WHEN s6 => next_state <= s7; WHEN s7 => next_state <= s0; END CASE; END PROCESS; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU6

The output process --output process PROCESS (state) BEGIN CASE state IS WHEN s0 => cnt <= "000"; WHEN s1 => cnt <= "001"; WHEN s2 => cnt <= "010"; WHEN s3 => cnt <= "011"; WHEN s4 => cnt <= "100"; WHEN s5 => cnt <= "101"; WHEN s6 => cnt <= "110"; WHEN s7 => cnt <= "111"; END CASE; END PROCESS; END one; --end of the architecture 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU7

Notes on code  Standard VHDL coding style An enumeration type for coding of the state Signals for state and state type 3 processes for modeling 1 st process – latching of next_state into state 2 nd process – generation of next_state  Here simple as no control signals 3 rd process – generation of output given the state – a Moore machine. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU8

The testbench  ENTITY is blank ENTITY testcnt3bit IS END testcnt3bit;  Declarative region of Arch ARCHITECTURE one OF testcnt3bit IS COMPONENT cnt3bit IS PORT (clk : IN bit; cnt : OUT bit_vector(2 downto 0)); END COMPONENT; FOR all : cnt3bit USE ENTITY work.cnt3bit(one); -- declare signal for stimulus and response of the DUT SIGNAL clk : bit; SIGNAL cnt : bit_vector(2 downto 0); BEGIN 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU9

In the testbench arch BEGIN -- As tb has clk will never go quiescent -- set up clk 50% duty cycle 10 ns period clk <= not clk AFTER 5 ns; -- instantiate component u1 : cnt3bit PORT MAP (clk,cnt); END one;  Testbench is very simple – apply the clk and instantiate the component. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU10

The VHDL simulation  Waveform shows binary counting output 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU11

When entered into Quartis  Automatically did a one-hot encoding 5 ALUTs – 8 registers – 4 pins 5 total combinational functions  Does a one hot encoding make sense? Class discussion 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU12

Compare to a binary encoding  Code the binary coding straight into VHDL  ENTITY is the same  Declarative region of the ARCHITECTURE Declarations are different ARCHITECTURE two OF cnt3bit IS SIGNAL state,next_state : bit_vector(2 downto 0); BEGIN 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU13

And in the processes -- latching of next_state PROCESS BEGIN WAIT UNTIL clk='1' AND clk'event; state <= next_state; END PROCESS; No difference here as both state and next_state are of the same type. (just bit_vector now) 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU14

Next State Process --next_state process PROCESS (state) BEGIN CASE state IS WHEN “000” => next_state <= “001”; WHEN “001” => next_state <= “010” ; WHEN “010” => next_state <= “011” ; WHEN “011” => next_state <= “100” ; WHEN “100” => next_state <= “101” ; WHEN “101” => next_state <= “110” ; WHEN “110” => next_state <= “111” ; WHEN “111” => next_state <= “000” ; END CASE; END PROCESS; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU15

Output Process  For this style the output process is simply assigning the state to the output as this is a Moore machine. This can be done with a concurrent signal assignment statement. cnt <= state; END one; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU16

Modify the testbench  In the declarative region add the 2 nd arch and cnt for the 2 nd arch  (note change in instantiation labels) ARCHITECTURE one OF testcnt3bit IS COMPONENT cnt3bit IS PORT (clk : IN bit; cnt : OUT bit_vector(2 downto 0)); END COMPONENT; FOR u1 : cnt3bit USE ENTITY work.cnt3bit(one); FOR binenc : cnt3bit USE ENTITY work.cnt3bit(two); -- declare signal for stimulus and response of the DUT SIGNAL clk : bit; SIGNAL cnt,cntbin : bit_vector(2 downto 0); BEGIN 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU17

After the begin BEGIN -- As tb has clk will never go quiescent -- set up clk 50% duty cycle 10 ns period clk <= not clk AFTER 5 ns; -- instantiate component u1 : cnt3bit PORT MAP (clk,cnt); binenc : cnt3bit PORT MAP (clk,cntbin); END one;  Note instantiation of 2 nd architecture which has output cntbin. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU18

Simulation  Result from simulation 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU19

Results from Quartis  Generating the FPGA for cnt3bitbin  This time encoding prevented choice of one-hot methodology.  Conclusion: Tool is not always right!! 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU20

A closer look  3 F/Fs  3 LUTs  4 pins 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU21

Controlling the binary assignment  Being able to control the binary assign results in more control for the designer and easier design of other counters.  Can result in more efficient use of FPGA resources. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU22

Time for live demo  Demo of code in Modelsim  Demo of setup in Quartis  Probably want to take note of steps and editing shortcuts. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU23

Lecture summary  HDL from code to simulation For the 101 sequence detector  Testbench for the sequence detector 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU24