Advanced Materials Research Center, AMRC, International SEMATECH Manufacturing Initiative, and ISMI are servicemarks of SEMATECH, Inc. SEMATECH, the SEMATECH logo, Advanced Technology Development Facility, ATDF, and the ATDF logo are registered servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners. Reliability assessment for new materials: Generation and activation of electrical defects in high-k gate stacks Gennadi Bersuker

Dielectric degradation: multilayer gate stack - Defect location: in high-k or IL? - Defect origin: intrinsic or process-related? - Defect generation mechanism: stress condition-dependent or ‘universal’?

Defects in interfacial SiO 2 P rocess-related  High-k-induced: O-vacancies & Hf impurities Defects in high-k As-grown: O-vacancies Stress generated – at high stress biases Polarons Characterization Combining electrical and physical techniques, and modeling

SILC evolution for monitoring breakdown TiN/ 3nm HfO 2 /2.1nm SiO 2 CVS 4.6V Stress-induced leakage current reflects on the formation of percolation path G.B., IRPS 2007

Probing SiO 2 traps SILCCharge Pumping Since CP probes IL, similar CP and SILC growth rates for each dielectric stack points to the same contributing defects in IL

Effect of stress voltage on reliability assessments 1.1nm SiO 2 / 3nm HfO 2 V stress = 2.4 V V stress = 4.1 V Low voltage High voltage Low voltage: activation of precursor defects in IL High voltage: defect generation in IL

High-k–induced O vacancies in SiO 2 IL: EELS Higher O deficiency  higher density of precursor defects (Si-Si)  converted by stress into electron traps Si- HfO2 SiO 2 Si Solid – as-deposited Dashed – after 1000C anneal Si Si/SiO 2 SiO 2 SiO 2 /HfO 2 Si L 2,3 -edge EELS G.B., JAP 2006 K. van Benthem, Pennycook

Metal/high-k-induced O defects in SiO 2 : ESR Metal/high-k process significantly enhances E’ center density in interfacial SiO 2 layer J. Ryan et al., APL nm HfO 2 /1nm SiO 2 /TiN+ 1000C PDA 3nm HfO 2 /1nm SiO 2 3nm HfO 2 /1nm SiO C PDA

SiO 2 (20Å) + HfO 2 (30Å)/TiN ºC/10s 12 SiO 2 (10Å) +HfO 2 (30Å)/TiN ºC/10s Metal/high-k-induced O defects in SiO 2 : ESR High-k-induced (process-related) generation of E’ centers is much more effective in thinner SiO 2 layers J. Ryan et al.

Fast interface trap generation: DCIV High-k devices show strong initial increase of both trapped charges and interface traps SiO 2 Neugroschel, IEDM 2006 High-k  D it VtVt DCIV measurements

Lenahan, IRW 2006 Hf defects in IL: spin dependent recombination Fast transient defect generation might be associated with Hf atoms in interfacial SiO 2 layer SiO 2 HfO 2 /SiO 2

Fast degradation: Hf in SiO 2 IL S. Rashkeev, INFOS 2005 Hf can diffuse through voids in SiO 2 SiO 2 Si Amorphous layers SiO 2 HfO 2 Si Hf “Regular” structure G.B., JAP 2006

Long-term instability: defects in SiO 2 Similar degradation rates in high-k stack and control SiO 2  same mechanism Neugroschel, IEDM 2006 Threshold voltageInterface states

Defect generation in high-k film Low V g : mostly reversible High V g : w/ continues degradation after discharge Stress time x1000 (sec) after discharge  V t (mV) 1.1nm SiO 2 / 3 nm HfO 2 V stress = 2.4 V Low stress voltage: reversible filling of pre-existing traps High voltage: trap generation V stress = 5 V

Defect generation in high-k: pulse measurements High-k Gate Defect generation at as-grown defect precursors

Trapping in amorphous high-k J. Gavartin, ECS 2006 Injected electron can trap via self-localization (polaron formation )  No defects needed to charge high-k film

Summary Interfacial SiO 2 layer: - Low bias stress: trap generation at as- processed precursor defects (O vacancies/Hf atoms) induced by high-k dielectric - High bias stress: new “conventional” defects High-k film: - Low bias stress: instability due to reversible electron trapping on as-processed defects (O- vacancies) or polaron formation(?) - High bias stress: defect generation at as- processed precursors: Defect nature? Mechanism?

Specifics of metal electrode/high-k dielectric gate stacks – Multi-layer dielectric stacks Interfacial SiO 2, high-k dielectric, metal/high-k interface – Ultra-short characteristic times Transient charging/discharging (relaxation) effects – High density of pre-existing defects O vacancies, under-coordinated metal and Si atoms Question applicability of SiO 2 test methodologies

New Materials Reliability Issues Reversible parameter instability – sensitive to measurement times; can be partially addressed by design Stress-dependent degradation mechanisms - test close to use conditions Strong process-dependent characteristics – reliability assessment requires extensive set of gate stacks of variety of compositions/processing