Innovation Center UFRGS/Microsoft Virtualization Instruction Set Architecture

Innovation Center UFRGS/Microsoft Development Team

Innovation Center UFRGS/Microsoft Development Team Researcher: Manuela Klanovicz Ferreira Advisor: Henrique Cota de Freitas

Innovation Center UFRGS/Microsoft Motivation

Innovation Center UFRGS/Microsoft Motivation Virtualization provide the isolation of multiple OSs stacks in their own Virtual Machines, so there are no data or instruction dependences Multi-core architecture can run each guest OSs really in parallel

Innovation Center UFRGS/Microsoft GOAL

Innovation Center UFRGS/Microsoft GOAL The goal of this work is develop an instruction set that offer support for virtualization in a multi-core environment. Visa First we have to run a workload in a multi-core model and analyse the operations that have to be improved. Each core uses virtualization technology present in single modern processors.

Innovation Center UFRGS/Microsoft Intel VT Intel VT is the Intel Virtualization Technology that provides hardware virtualization support in order to simplify the Virtual Machine Monitors (VMMs) and to increase the performance of virtualized systems Intel Virtualization Technology (VT) was chosen to be improved to multi-core systems because it has good documentation

Innovation Center UFRGS/Microsoft Intel VT: Instructions The operation instructions have the goal of simplify the context switchig between the Virtual Machines (Vms) and the Virtual Machine Monitor (VMM). Normal Operation VMX root (VMM) VMX non-root (VM) VMX active VMXON: enable VMX instructions VMLAUNCH: launch a new virtual machine (VM) VMCALL: switch the context to virtual machine monitor (VMM) VMXOFF: disable the VMX instructions VMRESUME: resume the VM execution

Innovation Center UFRGS/Microsoft Intel VT: Structures References the active VMCS, the VMCS that is running on CPU VMCS 1 VMCS 2 VMCS 3 VMM root ON Active VMCS Operation Mode VMX Operations CPU On CPU VMCS of VMM registers Stores the operation mode: root or non-root Shows if the VMX operation were ON or OFF References VMCS of Virtual Machine Monitor (VMM) Each launched VM has a VMCS to save its context, but only one will be the active VMCS of the physical processor

Innovation Center UFRGS/Microsoft ArchC ArchC is an ADL that can automatically generate simulators using the hardware description language SystemC

Innovation Center UFRGS/Microsoft Using ArchC Model Processor Description ArchC Framework Model Assembler Model Simulator Intel VT instructions Intel VT structures We modeled Intel VT instructions and structures and use the ArchC framework to generate the model assembler and simulator

Innovation Center UFRGS/Microsoft Testing

Innovation Center UFRGS/Microsoft Source of Assembly Test Design and Wrote the source of assembly test

Innovation Center UFRGS/Microsoft Compiling and Running the Test Model Processor Description ArchC Framework Model Assembler Model Simulator Source Assembly Test Binary Statistics Using the model assembler and model simulator we can generate statistics of test execution

Innovation Center UFRGS/Microsoft Test Results It is possible to check that with VMX instruction, the test has fewer executed instructions. In this case, the context switching is done through only one instruction The trace shows step-by-step each instruction execution. It is possible to add new traces in this model that show what a student needs for a specific work

Innovation Center UFRGS/Microsoft Events Participations

May of 2007 – ISCAS ( International Symposium on Circuits and Systems) October of 2007 – SBAC-PAD e WSCAD 2007 March of 2008 – ERAD 2008 in Sta Cruz do Sul June of 2008 – ISCA e WCAE ( Workshop on Computer Architecture Education ) in Beijing, China July of CSE 2008 in São Paulo Events Participations Use this model to simulate and understand virtualization are two contributions of VISA.

Innovation Center UFRGS/Microsoft Virtualization Instruction Set Architecture.