1 CSE370, Lecture 17 Lecture 17 u Logistics n Lab 7 this week n HW6 is due Friday n Office Hours íMine: Friday 10:00-11:00 as usual íSara: Thursday 2:30-3:20 CSE 220 íJosh: Thursday 3:30-4:20 CSE 002 n Midterm delayed until next Wednesday íWill cover material up to Friday’s lecture u Last two lectures n Registers, Counters, Counter Finite State Machines (FSM) n Sequential Verilog u Today n Another counter FSM n Timing issues íTiming terminology and issues and solutions (e.g. clock skew) íAsynchronous inputs and issues and solutions (e.g. debouncing)

2 CSE370, Lecture 17 Another 3-bit up counter: now with T flip flops 1. Draw a state diagram 2. Draw a state-transition table 3. Encode the next-state functions n Minimize the logic using K-maps 4. Implement the design

3 CSE370, Lecture Draw a state diagram bit up-counter

4 CSE370, Lecture Draw a state-transition table u Like a truth-table n State encoding is easy for counters  Use count value current statenext state bit up-counter

5 CSE370, Lecture Encode the next state functions T flip-flops TQ C2C1C0N2N1N0 T2 T1 T C1 C2 C0 T C1 C2 C0 T C1 C2 C0 T0 1 1 T0:= T1:= T2:= C0 C1 C0 1 Ti = 1 iff Ni ≠ Ci

6 CSE370, Lecture Implement the design TQTQTQ C0C1C2 CLK 1

7 CSE370, Lecture 17 The “WHY” slide u Timing issues n For sequential logic, “timing” is critical because for the same inputs, the output could be different at different times (like T-flip flops). In order to achieve desired outputs, timing has to be taken into consideration. n Transistors, chips, and even wires have their own delays. Because of this, nothing could ever be perfectly synchronized. It is important to understand how fast a clock can tick based on these delays and what the common issues are in making computers to run fast and accurately. n There are synchronous and asynchronous inputs. For example, typing on the keyboard, you are putting in asynchronous inputs to the computer. Asynchronous inputs can change the outputs immediately regardless of the clock state, and it is important to know how to handle that.

8 CSE370, Lecture 17 behavior of latch is the same unless input changes while the clock is high For most applications, it is not good to see Input changes instantaneously at the output CLK D Q ff Q latch Latches versus flip-flops DQ Q CLK DQ Q

9 CSE370, Lecture 17 The master-slave D (polarity reversed from previous class) DQ CLK Input Master D latch DQ Output Slave D latch master-slave D flip-flop Because of the timing issue, it was good to use two latches as master-slave configuration or use one flip-flop.

10 CSE370, Lecture 17 For most applications, it is not good to see Input changes instantaneously at the output CLK D Q ff Q latch’ Q masterslave Master-Slave D implements D flip-flop DQ Q CLK DQ Q

11 CSE370, Lecture 17 Timing terminology and constraints for a FF n Setup time t su : Amount of time the input must be stable before the clock transitions high (or low for negative-edge triggered FF) n Hold time t h : Amount of time the input must be stable after the clock transitions high (or low for negative-edge triggered FF) n Clock width t w : Minimum clock width that must be met in order for FF to work properly n Propagation delays t p-lh and t p-hl : Propagation delay (high to low, low to high) (longer than hold time) thth twtw t p-lh t p-hl t su D CLK Q th th t su DQ Q CLK

12 CSE370, Lecture 17 Cascading flip-flops u Flip-flop propagation delays exceed hold times n Second stage commits its input before Q0 changes In Q0 Q1 Clk t su t p-hl thth t su thth t p-lh IN CLK Q0 Q1 DQDQ > > Order can’t be reversed else Q1 will not have its required hold time t p-hl, t p-lh > t h t p + t su < t cycle

13 CSE370, Lecture 17 Side note: Clock skew u Goal: Clock all flip-flops at the same time n Difficult to achieve in high-speed systems íClock delays (wire, buffers) are comparable to logic delays n Problem is called clock skew n Avoiding clock skew: design identical delays Original state: IN = 0, Q0 = 1, Q1 = 1 Next state: Q0 = 0, Q1 = 0 (should be Q1 = 1) CLK0 clocks first flipflop CLK1 clocks second flipflop CLK1 should align with CLK0, but is delayed due to clock skew IN Q0 Q1 CLK0 CLK1

14 CSE370, Lecture 17 System considerations u Use edge-triggered flip-flops wherever possible n Avoid latches n Most common: Master-slave D u Basic rules for correct timing n Clock flip-flops synchronously (all at the same time) íNo flip-flop changes state more than once per clock cycle íFF propagation delay > hold time n Avoid mixing positive-edge triggered and negative-edge triggered flip-flops in the same circuit

15 CSE370, Lecture 17 u Asynchronous n State changes occur when state inputs change n Feedback elements may be wires or delays u Synchronous n State changes occur synchronously n Feedback elements are clocked Asynchronous versus synchronous Clock Combinational Logic SynchronousAsynchronous

16 CSE370, Lecture 17 Asynchronous inputs u Clocked circuits are synchronous n Circuit changes state only at clock edges n Signals (voltages) settle in-between clock edges u Unclocked circuits or signals are asynchronous n No master clock n Real-world inputs (e.g. a keypress) are asynchronous u Synchronous circuits have asynchronous inputs n Reset signal, memory wait, user input, etc. n Inputs “bounce” n Inputs can change at any time íWe must synchronize the input to our clock íInputs will violate flip-flop setup/hold times

17 CSE370, Lecture 17 Debouncing u Switch inputs bounce n i. e. don’t make clean transitions u Can use RS latch for debouncing n Eliminates dynamic hazards n “Cleans-up” inputs R S Q Q' 3.3V 0V 3.3V 0V

18 CSE370, Lecture 17 Synchronizer failure u Occurs when FF input changes near clock edge n Input is neither 1 or 0 when clock goes high n Output may be neither 0 or 1 íMay stay undefined for a long time n Undefined state is called metastability logic 0 logic 1 D CLK Q

19 CSE370, Lecture 17 Minimizing synchronizer failures u Failure probability can never be zero n Cascade two (or more) flip-flops íEffectively synchronizes twice íBoth would have to fail for system to fail D D Q asynchronous input synchronized input Clk Q

20 CSE370, Lecture 17 Handling asynchronous inputs u Never fan-out asynchronous inputs n Synchronize at circuit boundary n Fan-out synchronized signal DQ DQ Q0 Clock Q1 Async Input DQ DQ Q0 Clock Q1 Async Input DQ Synchronizer

21 CSE370, Lecture 17 Summary: Timing issues with asynchronous inputs u For sequential logic circuits, timing issues have to be considered. u Inputs are often asynchronous and can cause problems. u Different amount of delay at different part of the circuit can cause problems also. u Solutions: n Cascade flip flops in series n Incorporate RS latch for debouncing n Design to keep timing alignment in mind (length of wires, etc)