Mahapatra-Texas A&M-Fall'001 How to plan on project work? An attempt to consolidate your thought to gear up project activities

Mahapatra-Texas A&M-Fall'002 Major grade Projects Suggested areas: –MP3 decoder implementation using codesign approach –Use of HDLC core and design Ethernet interface –Application specific codesign (two projects) –Check if there is another codesign problem

Mahapatra-Texas A&M-Fall'003 Alert to make use of.. Suitable model: if not given, may develop one specification: use appropriate language(s) including HDL, state diagram, C or its class Target architectures: controller and/or FPGAs or both Partitioning and simulation

Mahapatra-Texas A&M-Fall'004 Make use of... Core: open source cores available for some building blocks Implementation: only after making sure that the design is validated

Mahapatra-Texas A&M-Fall'005 Suitable models Consider tool(s) that you are accessible to may borrow open tools if one is available analyze why certain model is better than other for your application Discussions: open

Mahapatra-Texas A&M-Fall'006 Languages Believe that most designs require C, Verilog or VHDL as building components Estrel is required if Polis is in use For cosimulation using C and Verilog: VerilogPLI is required for interfacing between the language. Complex designs require multi-language interfaces

Mahapatra-Texas A&M-Fall'007 Target Architectures A controller such as Motorola 68K class as supported by the Ptolemy (?). FPGAs: Xilinx 4000 series (4010, 4028), Spartan (2 pieces), Vertex board (one) capable of handeling 800K gates design. –Vertex board is capable of interfacing several devices such as monitor, network, audio/video and parallel ports

Mahapatra-Texas A&M-Fall'008 Target architectures Stand alone FPGA boards: small commercial boards available with serial or parallel ports for download can devise your own FPGA board too to go with other design: but know the pin details from the data book in the lab, wire-wrap. DSP board: TMS is one of the highend DSP board from Texas Instruments. –Capable of programming in C, –run several benchmarks from open sources –full supported software tools available

Mahapatra-Texas A&M-Fall'009 Partitioning Functional May use GCLP algorithm for your problem can modify the algorithm, choose varieties of partitioning combinations and check for the best verification: cosimulation, emulation, Ptolemy/Polis, Library: important to know the hw and sw implementation overhead either from given sources or build one Research problems

Mahapatra-Texas A&M-Fall'0010 Cores Several open sources PCI, HDLC are free licences to the lab, can look for other sources too look for benchmarks on available cores Level: cores are mostly in gate level, some times - behavioral level is better for making changes, can use existing codes on interface such as serial/parallel: may not reinvent the wheel Share the cores too.

Mahapatra-Texas A&M-Fall'0011 Implementation Complete the projects only after combining hw and sw in its implementation. Results: –timing details for each possible partitioning effects and the optimum result seen by you –area information from synthesis level verification –suitable reports with all developed codes and references

Mahapatra-Texas A&M-Fall'0012 Actions MP3 decoder: find suitable algorithms Look at the Vertex platform and DSP hw/sw details search DSP benchmarks (ask Rahul) Lay out a plan based on today’s discussions and approve it from instructor. Let us know if you need any resources for your projects Use your lab time wisely.

Mahapatra-Texas A&M-Fall'0013 Discussions Open for questions and suggestions Will continue until semester end