Introduction to structured VLSI Projects 4 and 5 Rakesh Gangarajaiah

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Presentation transcript:

Introduction to structured VLSI Projects 4 and 5 Rakesh Gangarajaiah

Objectives Understand how to use the IP generator Designing an interface with a memory and system integration Fixed point programming and algorithm development from Matlab to Hardware implementation Optimizing design for hardware resource constraints

Overview of the system GRADE 4 GRADE 5

VGA controller

Understand the VGA controller design. –Modify parts of it to control the VGA display –Create a driver for one 7 segment number display and re-use it to create others –Remember that the square root will need an additional 7 segment display

VGA controller

Project 4 - Calculator with Memory Objectives: Integrate a 8k bit, 8bit wide RAM module to your ALU Create/Update the VGA controller to display inputs and outputs on VGA screen Input operands and operator from keyboard, store in RAM, fetch data and display results on VGA screen Input operands are unsigned in the range of 0 to 255, but the result will be signed

Xilinx LogiCoreIP generator Read about the IP generator Instantiate the memory following instructions from the manual

Testing the RAM

Expected operation : Data fill Enter data from keyboard Press data latch button Addr 0 10 Addr 1 + Addr 2 98 Addr 3 54 Addr 4 * Addr 5 3 Direction of data fill Addr 6 30 Addr 7 - Addr 8 6

Expected operation : Data retrieve and display At every press of the key Pop data Display result Addr 0 10 Addr 1 + Addr 2 98 Addr 3 54 Addr 4 * Addr 5 3 Addr 6 30 Addr 7 - Addr – 030 = * 054 = +162 VGA SCREEN Direction of data POP

Expected operation: Enter more operands Should be able to accept new inputs In the middle of data display Enter operands from keyboard Press latch data Addr 0 10 Addr 1 + Addr 2 98 Addr 3 7 Addr 4 * Addr 5 7 The next display on pressing the key should be 007*007 = +049 VGA SCREEN 007 * 007 = * 054 = +162

Expected operation :

Project 5: ALU with square root

Objectives Develop an algorithm for square root –Implement in Matlab and verify with RTL output Display result accurate to atleast 3 decimal digits –Sqrt(111) = –Sqrt(121) = Do not use a look up table!! The final implementation should be within a specified hardware resource utilization constraint. (More details in the manual)

Square root unit Different algorithms available to compute the square root –Use Google, Wikipedia to find algorithms Iterative algorithm –Needs a simple state machine –Make sure the decimal point is moved properly between states Some of the algorithms need a division operation –Use an IP to generate division outputs Contact the TA before you finalize your algorithm

Hardware utilization Multipliers and dividers are usually needed for iterative algorithms –Re-use as many as possible Synthesize sqrt unit separately to enable the TA’s to check that you have met the resource constraints

Divider Use the LogiCore IP generator to generate a divider –Discuss with TA about your choices of internal signal widths before starting 3 digits in decimal corresponds to 10 bits in binary Test the divider unit separately before integrating

Integration Integrate the square root into the ALU unit Final implementation should be able to accept square root as one of the operands (Use the key of your choice to indicate square root) and store it in the memory Should display the results when enter keys are pressed just like in Project 4.