CASTNESS'07 Rome, Italy January 2007 Programming Models and Hardware Dependent Software Abstraction for Multi-Processor SoC Ahmed A. Jerraya TIMA Laboratory 46 Avenue Felix Viallet, Grenoble Cedex France Tel: , Fax:

CASTNESS' Ahmed Jerraya TIMA Laboratory Techniques of Informatics and Microelectronics for computer Architecture CNRS – INPG – UJF ~ 140 persons (incl. CMP) Research  Concurrent Integrated Systems, M. RENAUDIN  System Level Synthesis, A. JERRAYA, F. PETROT  MiCro & Nano Systems, S. BASROUR & B. COURTOIS  Reliable Mixed-signal Systems, S. MIR  QuaLiFication of Circuits, R. VELAZCO  Verification and Modeling of Digital Systems, D. BORRIONE Service: CMP  500 institutions, 60 countries, ICs, MEMS, CAD, Kits  CMOS.12µ ST

CASTNESS' Ahmed Jerraya System-Level Synthesis Group (SLS)  Research area :  System on chip design  Objectives :  Decrease the design time through new design methodologies and tools  Methods :  Theoretical work :  Hardware/software interfaces  Heterogeneous components based design  Applications to understand the needs: Divx, MJPEG, H264  Validation of research in collaboration with industry CPUIPDSP MPEG4 Encoder NoC

CASTNESS' Ahmed Jerraya System-Level Synthesis (SLS) Staff (25):  Group Leaders: A. Jerraya, F. Pétrot  Permanent Staff :P. Amblard, A. Bouchhima, L. Kriaa F. Rousseau, W. Youssef, N. Zergainoh  Ph.D. students: Y. Atat, Y. Cho, A. Chureau, P. de Massas, P. Gerin, X. Guérin, S. Han, A. Kouadri Mostéfaoui, M. Oyamada, K. Popovici, B. Senouci, H. Shen  Industrial Ph.D.:M. Fiandino, R. Lemaire, Ch. Sahnine Contracts:  Industrial cooperation  National & EC Funding: MEDEA, IST, RNRT, ITEA

CASTNESS' Ahmed Jerraya Acknowledgement Prof F. Pétrot, Dr. F. Rousseau Dr. A. Bouchhima, Dr W Youssef PhD Students  A. Chureau  K. Popovici  H. Shen  X. Guérin  P. Gerin

CASTNESS' Ahmed Jerraya Summary Context  MPSoC design: Abstract software (e.g.: CORBA, Simulink µCCM) and heterogeneous hardware (DSP, RISC) Performance/cost constraints  Time-to-market: Reuse HW Platforms and SW components Problems  Architecture exploration for mapping of SW components on Hardware platform  Difficult Hardware dependent Software debug The Challenge: Fast and efficient mapping of software components to hardware platform SW IPs Target Hardware platform SW IP Component (F3) SW IP Component (F4, F6) SW IP Component (F2, F5) SW IP Component (F1) DSP #1 C Mhz DSP #2 C Mhz GPP MPC Mhz FPGA Bus Ethernet Contrôle CAN CNA Contrôle du signal radio Application SW HDS Binary SW

CASTNESS' Ahmed Jerraya Outline 1.- Programming Models: the Bridge between Hardware and Software 2.- Application-Specific Programming Models to Handle MPSoC 3.- Programming Models at Different Abstraction Levels 4.- Next Generation Design Flow Based on Programming Models 5.- Summary

CASTNESS' Ahmed Jerraya Context: Heterogeneous MPSoC Hardware Node Software Node Communication Network Multi-Thread application Operating System Specific I/O HAL CPU DMA MEM bridge Network interface Hardware Co-processor HW/SW Interface Model HW PROTOCOL SW interface Heterogeneous MPSoC  Hardware nodes for performance  Software nodes for flexibility  Communication network A programming model abstracts HW-SW interfaces for SW design. Software node: Specific CPU subsystem  GPP, DSP, ASIP,...  I/O and memory architecture Layered SW architecture  Application code (threads)  Hardware dependent software

CASTNESS' Ahmed Jerraya Programming Model: The Classical Solution to Abstract HW-SW Interfaces Abstract HW model for SW design  Programming language with implicit primitives (e.g. module hierarchy & threads in SystemC)  API: Application Programming Interface (MPI, Posix Threads)  Simulation model (MPICH, Linux) Used by SW community to free the SW designer from knowing HW details. Facilitate porting of application SW over different architectures that support the same API. SW modules API SW modules API SW modules API HW dependent SW (HDS) HW architecture Execution Environment SW 1 SW 2 SW n... Implementation Simulation

CASTNESS' Ahmed Jerraya SW Reuse Based on Programming Model (API): MPEG4 HAL API HDS x CPU x Comm. network SW API HDS y CPU y Communication network IP 1 IP 3 IP 2 API MPEG4 API IP Executing same SW on different architectures using different CPUs HDS = Hardware dependent Software (OS, HAL, Specific I/O)

CASTNESS' Ahmed Jerraya Defining HW-SW Interfaces Application SW Designer: A set of system calls used to hide the underlying execution platform. Also Called Programming Model HW designer: A set of registers, control signals and more sophisticated adaptors to link CPU to HW subsystems. System SW designer: Low level SW implementation of the programming Model for a given HW architecture. CPU is the ultimate HW-SW Interface Sequential scheme assuming HW is ready to start low level SW design SoC Designer  Abstracts both HW and SW in addition to CPU  HW-SW interfaces tradeoff Sequential SW program … Call HW (x, y, z) x y z HW function wait start … API CPU (local Architecture) HW Dependant SW CPU Bus HW-Adaptation Start done x y z CTRL HW-SW Interfaces

CASTNESS' Ahmed Jerraya Outline 1.- Programming Models: the Bridge between Hardware and Software 2.- Application-Specific Programming Models to Handle MPSoC 3.- Programming Models at Different Abstraction Levels 4.- Next Generation Design Flow Based on Programming Models 5.- Summary

CASTNESS' Ahmed Jerraya Classical HW/SW Interfaces Abstraction Models : The GAPS Functional specification Partition ning Software design Hardware design Integration ISA/RTL Hardware/Software discontinuity Correction cycle Virtual Prototype System Level Early HW/SW integration Software Sub-System Software Thread 1 Software Thread 2 Hardware Binary SW Appli OS HAL ISS FIFO IT Ctrl MEM HW Software Sub-System Software Thread 1 Software Thread 1 Hardware GAP Fully implicit HW/SW Interface Fully explicit HW/SW Interface Abstract HW/SW Interface

CASTNESS' Ahmed Jerraya Parallel Programming Models: The mixed HW-SW interfaces GAP SoC Design Distributed SW Design RTL (Verilog, BinSW) Virtual Prototype (RTL HW, BinSW, e.g. SystemC) MPIRT-CORBA CORBA SDL Programming Model SW: ALL CPU imple- mentation SW: ALL RTL HW CPU orga- nization High Level Synchro- nisation HW: NONE Communi- cation HW: NONE - Concurrency - Threading HW: NONE HW-SW Interfaces Explicit concepts Mixed Abstract HW-SW Interfaces models

CASTNESS' Ahmed Jerraya Parallel Programming Models for MPSoC RTL (Verilog, BinSW) Virtual Prototype (RTL HW, BinSW, e.g. SystemC) MPIRT-CORBA CORBA SDL SoC Design Distributed SW Design SW: ALL CPU imple- mentation SW: ALL RTL HW CPU orga- nization Transaction Accurate (TLM HW, TLM SW: Abstract CPU+HAL) Virtual Architecture (Abstract HW, HL SW: Threads & Abstract OS + CPU SS) - OS - Specific I/O - CPU SS - Abstract Bus - Explicit HW modules Communication/ Computation Modules Abstract Interconnect Synchro- nisation HW: NONE Communi- cation HW: NONE - Concurrency - Threading HW: NONE Programming Model HW-SW Interfaces Explicit concepts HDS development platform SW application development platform

CASTNESS' Ahmed Jerraya Outline 1.- Programming Models: the Bridge between Hardware and Software 2.- Application-Specific Programming Models to Handle MPSoC 3.- Programming Models at Different Abstraction Levels 4.- Next Generation Design Flow Based on Programming Models 5.- Summary

CASTNESS' Ahmed Jerraya Wires API HW modules Application software HW modules Hardware Abstract SW Execution engine Abstract comm. channels or abs. channels  SoC Model with Abstract HW-SW Interfaces  Separate HW and SW design  Better HW & SW reuse. Key Innovation to Higher Level HW/SW Interface Abstraction: from CPU to SW Execution Subsystem HW platform Hardware HW modules Hardware interconnects CPU Hardware Application Software +  Traditional view of SoC  CPU is HW-SW interface.  SW validation assumes HW ready. HW & inf. to CPU Hardware Dependent SW HW-SW interfaces to be abstracted  HW-SW Interfaces to be abstracted  Require to model HW, SW and CPU  Allow new architecture trade-off. BootMemBank (Mem) CtrlCPU TaskMgr

CASTNESS' Ahmed Jerraya Interface Modeling at Transaction Accurate Level To be abstracted  HAL software layer  Details of CPU subsystem SW interface : HAL API  Context switch  Synchronization (e.g. spin lock)  IO Read/Write HW interface : HW protocol  Bus Protocol,…  Specific HW interface (FIFO) CPU DMA MEM bridge Network interface Hardware Co-processor Multi-Thread application Operating System Specific I/O HAL Hardware HW/SW Interface At Transaction Accurate Level HW PROTOCOL HAL API

CASTNESS' Ahmed Jerraya Services for HW/SW Interfaces Adaptation Both HW and SW interfaces are modeled as set of services (provided/required) HW Hyb SW Software Sub-System Software Thread 1 Software Thread 2 Hardware Component based interface adaptation  Software elements  Hardware elements  Hybrid elements

CASTNESS' Ahmed Jerraya HARDWARE SOFTWARE Motion JPEG application : System Level Model High Simulation speed Easiest functional validation  No Operating System details  No details on communications 6 software and 2 hardware tasks Execution model synchronized with communications TRAFFIC GENERATOR VIDEO OUT DEMUX VLD IQ ZZ IDCT LIBU Communication channel thread

CASTNESS' Ahmed Jerraya Motion JPEG application : Virtual Prototype Model Detailed communications Performances precision  Fastidious Operating System validation  Very slow simulation Binary SW Appli Mutek OS HAL ISS FIFO IT Ctrl MEM TG VCI Cross bar VIDEO Software tasks executed on a POSIX compliant OS: MUTEK Software interpreted by the target processor ISS Rest of the system at RTL level HW/SW Interface At Transaction Accurate Level HW PROTOCOL HAL API

CASTNESS' Ahmed Jerraya HW PROTOCOL HAL API Motion JPEG application: Transaction Accurate Model Pure software elements  CONTEXT  INTERRUPT Pure Hardware  VCI FIFO Hybrid elements  CROSSBAR  VCI WRAPPER  EXEC_UNIT  … OS INIT SMP THIS COUNT IO_ACCESS READ WRITE DIAGNOSTIC CONSUME MEM VCI_WRAPPER FIFO XBAR CXT INIT SWITCH SPIN LOCK UNLOCK CONTEXT EXEC_UNIT HS_WRITE REQACKDATA IT MASK UNMASK IT_CTRL INTERRUPT SPIN HS_READ REQACKDATA

CASTNESS' Ahmed Jerraya Interfaces Modeling at Virtual Architecture Model Apply the proposed approach to other abstraction level : CPU DMA MEM bridge Network interface Hardware Co-processor Multi-Thread application Operating System Specific I/O HAL Hardware HW/SW Interface At Transaction Accurate Level HW interface SW interface HW/SW Interface At Virtual Architecture Level HW interface SW interface  Virtual Architecture, abstract the operating system and the specific communication HW/SW interface design automation to enable :  Architecture exploration.  Refinement

CASTNESS' Ahmed Jerraya Experiment Simulations 3 simulations MJpeg Appli Host OS (LINUX) POSIX API SW view of HW POSIX API System Level MJpeg Appli POSIX API MUTEK OS T.A. Model HW PROTOCOL POSIX API Hardware Transaction Accurate MJpeg Appli POSIX API MUTEK OS HAL API HAL (sparc) ISS + Sub-System Hardware HW PROTOCOL Virtual Prototype 235s/frame (Fully explicit HW-SW interfaces) Same OS code in T.A. and V.P. Same SW application code in the 3 models Same SW 0.017s/frame (Fully implicit HW-SW interfaces) X 701.2s/frame (Abstract HW-SW interfaces) X 200

CASTNESS' Ahmed Jerraya Outline 1.- Programming Models: the Bridge between Hardware and Software 2.- Application-Specific Programming Models to Handle MPSoC 3.- Programming Models at Different Abstraction Levels 4.- Next Generation Design Flow Based on Programming Models 5.- Summary

CASTNESS' Ahmed Jerraya HW and SW Design Approaches Using high level HW-SW Interfaces models SW Debug Application SW Design API Time Classical HW & SW design approaches for computers HDS Design HW Design Debug and integration HW Design Application SW and HDS Design HW & SW Design Approaches for SoC HW-SW Interfaces design Application SW Design Application SW development Platform (VA) HW Design HDS development Platform(TA) Time saving Debug/ Performances validation

CASTNESS' Ahmed Jerraya Conclusions: Programming Models for MPSoC Abstract HW-SW Interfaces to enable Higher than RTL design A platform for early application SW & HDS validation Better match between HW & SW Is an opportunity for new HW-SW codesign approaches and architecture Exploration

CASTNESS' Ahmed Jerraya Thank You