Datta1 Routing for Reliability in Molecular Diode-based Programmable Nanofabrics Kushal Datta, Arindam Mukherjee and Arun Ravindran Department of Electrical.

Slides:

Advertisements

Similar presentations

Inter-Iteration Scalar Replacement in the Presence of Control-Flow Mihai Budiu – Microsoft Research, Silicon Valley Seth Copen Goldstein – Carnegie Mellon.

Advertisements

NanoFabric Chang Seok Bae. nanoFabric nanoFabric : an array of connect nanoBlocks nanoBlock : logic block that can be progammed to implement Boolean function.

EECE **** Embedded System Design

A Graph-Partitioning-Based Approach for Multi-Layer Constrained Via Minimization Yih-Chih Chou and Youn-Long Lin Department of Computer Science, Tsing.

EELE 367 – Logic Design Module 2 – Modern Digital Design Flow Agenda 1.History of Digital Design Approach 2.HDLs 3.Design Abstraction 4.Modern Design Steps.

NATIONAL INSTITUTE OF SCIENCE & TECHNOLOGY Presented by: Susman Das Technical Seminar Presentation FPAA for Analog Circuit Design Presented by Susman.

12004 MAPLD/1002??? When Should You and When Should You Not Use VHDL? Richard B. Katz NASA Office of Logic Design 2004 MAPLD International Conference September.

1 Recursive Learning Madhurima Maddela. ELEC /26/052 Decision Tree Traditionally used to branch and bound in the search space to generate test.

Lecture 26: Reconfigurable Computing May 11, 2004 ECE 669 Parallel Computer Architecture Reconfigurable Computing.

ENGIN112 L38: Programmable Logic December 5, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 38 Programmable Logic.

Spring 07, Jan 16 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Introduction Vishwani D. Agrawal James J. Danaher.

A High Performance Application Representation for Reconfigurable Systems Wenrui GongGang WangRyan Kastner Department of Electrical and Computer Engineering.

Nanotechnology: Spatial Computing Using Molecular Electronics Mihai Budiu joint work with Seth Copen Goldstein Dan Rosewater.

Reconfigurable Computing (EN2911X, Fall07)

Physical Design Outline –What is Physical Design –Design Methods –Design Styles –Analysis and Verification Goal –Understand physical design topics Reading.

Compiling Application-Specific Hardware Mihai Budiu Seth Copen Goldstein Carnegie Mellon University.

ENEE 408C Lab Capstone Project: Digital System Design Spring 2006 Class Web Site:

NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture Wei Zhang†, Li Shang‡ and Niraj K. Jha†

LabVIEW Design of Digital Integrated Circuits FPGA IC Implantation.

Techniques and Algorithms for Fault Grading of FPGA Interconnect Test Configurations Mehdi Baradaran Tahoori and Subhasish Mitra IEEE Transactions on Computer-Aided.

1 Chapter 7 Design Implementation. 2 Overview 3 Main Steps of an FPGA Design ’ s Implementation Design architecture Defining the structure, interface.

CS 151 Digital Systems Design Lecture 38 Programmable Logic.

Introduction to FPGA’s FPGA (Field Programmable Gate Array) –ASIC chips provide the highest performance, but can only perform the function they were designed.

Chapter 5 Boolean Algebra and Reduction Techniques William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education,

General FPGA Architecture Field Programmable Gate Array.

Electronic Design Automation. Course Outline 1.Digital circuit design flow 2.Verilog Hardware Description Language 3.Logic Synthesis –Multilevel logic.

Trigger design engineering tools. Data flow analysis Data flow analysis through the entire Trigger Processor allow us to refine the optimal architecture.

1 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) ECpE 583 Reconfigurable Computing Lecture.

Building Cad Prototyping Tool for Emerging Nanoscale Fabrics Catherine Dezan Joined work between Lester( France.

FPGA Switch Block Design Dr. Philip Brisk Department of Computer Science and Engineering University of California, Riverside CS 223.

CAD for Physical Design of VLSI Circuits

Combinational Logic Design BIL- 223 Logic Circuit Design Ege University Department of Computer Engineering.

1 Moore’s Law in Microprocessors Pentium® proc P Year Transistors.

CSE 494: Electronic Design Automation Lecture 2 VLSI Design, Physical Design Automation, Design Styles.

Tools - Implementation Options - Chapter15 slide 1 FPGA Tools Course Implementation Options.

COE 405 Design and Modeling of Digital Systems

ELEC692/04 course_des 1 ELEC 692 Special Topic VLSI Signal Processing Architecture Fall 2004 Chi-ying Tsui Department of Electrical and Electronic Engineering.

Introduction to FPGA Created & Presented By Ali Masoudi For Advanced Digital Communication Lab (ADC-Lab) At Isfahan University Of technology (IUT) Department.

Han Liu Supervisor: Seok-Bum Ko Electrical & Computer Engineering Department 2010-Feb-2.

Incremental Placement Algorithm for Field Programmable Gate Arrays David Leong Advisor: Guy Lemieux University of British Columbia Department of Electrical.

Chapter 5 Boolean Algebra and Reduction Techniques 1.

1 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) CPRE 583 Reconfigurable Computing Lecture 5: 9/7/2011.

Lopamudra Kundu Reg. No. : of Roll No.:- 91/RPE/ Koushik Basak

EE 5900 Advanced Algorithms for Robust VLSI CAD, Spring 2009 Combinational Circuits.

ELE 523E COMPUTATIONAL NANOELECTRONICS W10: Defects and Reliability, 16/11/2015 FALL 2015 Mustafa Altun Electronics & Communication Engineering Istanbul.

FPGA CAD 10-MAR-2003.

In-Place Decomposition for Robustness in FPGA Ju-Yueh Lee, Zhe Feng, and Lei He Electrical Engineering Dept., UCLA Presented by Ju-Yueh Lee Address comments.

Combinational Logic Design. 2 Combinational Circuits A combinational logic circuit has: ♦ A set of m Boolean inputs, ♦ A set of n Boolean outputs ♦ n.

© PSU Variation Aware Placement in FPGAs Suresh Srinivasan and Vijaykrishnan Narayanan Pennsylvania State University, University Park.

Architecture and algorithm for synthesizable embedded programmable logic core Noha Kafafi, Kimberly Bozman, Steven J. E. Wilton 2003 Field programmable.

ASIC/FPGA design flow. Design Flow Detailed Design Detailed Design Ideas Design Ideas Device Programming Device Programming Timing Simulation Timing Simulation.

LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block S/V block I/O Cell.

Combinational Logic Design. 2 Combinational Circuits A combinational logic circuit has: ♦ A set of m Boolean inputs, ♦ A set of n Boolean outputs ♦ n.

1 Architecture of Datapath- oriented Coarse-grain Logic and Routing for FPGAs Andy Ye, Jonathan Rose, David Lewis Department of Electrical and Computer.

Placement study at ESA Filomena Decuzzi David Merodio Codinachs

ELEC 7770 Advanced VLSI Design Spring 2016 Introduction

MAPLD 2005 Reduced Triple Modular Redundancy for Tolerating SEUs in SRAM based FPGAs Vikram Chandrasekhar, Sk. Noor Mahammad, V. Muralidharan Dr. V. Kamakoti.

CSCI-100 Introduction to Computing

Architecture Synthesis for Cost Constrained Fault Tolerant Biochips

Incremental Placement Algorithm for Field Programmable Gate Arrays

ELEC 7770 Advanced VLSI Design Spring 2014 Introduction

Verilog to Routing CAD Tool Optimization

ELEC 7770 Advanced VLSI Design Spring 2012 Introduction

ELEC 7770 Advanced VLSI Design Spring 2010 Introduction

CPRE 583 Reconfigurable Computing

Chapter 3 – Combinational Logic Design

ECE 699: Lecture 3 ZYNQ Design Flow.

HIGH LEVEL SYNTHESIS.

A New Hybrid FPGA with Nanoscale Clusters and CMOS Routing Reza M. P

Reconfigurable Computing (EN2911X, Fall07)

Presentation transcript:

datta1 Routing for Reliability in Molecular Diode-based Programmable Nanofabrics Kushal Datta, Arindam Mukherjee and Arun Ravindran Department of Electrical and Computer Engineering University of North Carolina at Charlotte MAPLD 2005/1031

datta2 Nanofabric Architecture Switch Block Diode-based CMU Architecture NanoFabrics: Spatial Computing Using Molecular Electronics Seth Copen Goldstein and Mihai Budiu Proc. of The 28th Annual International Symposium on Computer Architecture, June Nano Block CMOS on Molecular: CMOL MAPLD 2005/1031

datta3 Circuit Primitives AB f = A. B AB f = A+B AB V dd f = A. B ff f MAPLD 2005/1031

datta4 Circuit Primitives AB V dd f = A+B A A A A V dd f MAPLD 2005/1031

datta5 Nano Electronic Design Automation An example Problem Formulation Given –A logic design –A nanofabric Constraints –Entry and exit directions of signals in nano/switch blocks –Size of nano and switch blocks Minimize –The total number of diodes and switches used  Improve robustness MAPLD 2005/1031

datta6 Nano EDA Flow Optimized Nano Layout Routing Space Search VHDL Code Boolean Function net list Decomposed List Packed List Placed Gate Array PKS + script Flow Map VPACK VPR Placed Nanofabric Alternate Routes Our IP optimizer Map FPGA Nanofabric MAPLD 2005/1031

datta7 Placement Use a standard algorithm of VPR and get a placed file. Modify the placed file. Modification of the placed file involves considering all the possible 12 transformations and deriving equations for them. Implement a mapping program for this. MAPLD 2005/1031

datta8 Placement Sample placed file Equations based on the transformation from the placed file for gate array to the placed file for the nano fabric: x = 2x – z y = 2y – z y A B C D E F G H x Slice number (z) MAPLD 2005/1031

datta9 Global Routing Problem Formulation Required AND gate literals enter from West (W) side Required OR gate literals enter from North (N) side If (R (l i ) = W) & (E (l i )=N) 1 extra diode If (R (l i ) = N) & (E (l i )=W) 1 extra diode lili lili lili lili V dd MAPLD 2005/1031

datta10 Problem Formulation A C B S2S2 S1S1 l3l3 l2l2 l1l1 MAPLD 2005/1031

datta11 Future Design Flow VLSI-inspired Nano-EDA Bio-inspired Nano-EDA  High Fault Tolerance  Low Power Optimized Nano Layout Routing Space Search VHDL Code Boolean Function net list Decomposed List Packed List Placed Gate Array PKS + script Flow Map VPACK VPR Placed Nanofabric Alternate Routes Our IP optimizer Map FPGA Nanofabric MAPLD 2005/1031

datta12 Integrate Placement with Global and Detailed Routing - Improve Fault Tolerance Simulated Annealing Moves : –Select switch and nano blocks for placement –Select switch and nano blocks for global routing –Select entry and exit edges for global routing –Select exact entry and exit row/column in a block fro detailed routing MAPLD 2005/1031