Subsystem Design 2 EE213 VLSI Design This section contains some notes on logic implementation and more complex gates etc. Full details are in Pucknell.

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Presentation transcript:

Subsystem Design 2 EE213 VLSI Design This section contains some notes on logic implementation and more complex gates etc. Full details are in Pucknell and Eshraghian pages 146 to 159.

Logic Implementation When designing digital circuits with MOS technology, there are 2 basic approaches in building logic circuits Switch Logic Gate / Restoring Logic

Switch Logic Based on pass transistors or transmission gates Fast for small arrays No static current from supply lines Logic based on relay logic Easy implement basic AND / OR connections Pass transistor logic levels get degraded by Vt effects Transmission gates do not suffer from Vt effects but –more complex –more area –potential fabrication problems –requires true and complement of gate signal No pass transistor gate may be driven through one or more pass transistors

Switch Logic Levels See Kamran and Eshraghian pages for discussion on logic levels –Logic 1 degraded for n-type pass –Logic 0 degraded for p-type pass –Transmission gates - good logic levels –Loss of logic level 1 if the gate of a pass transistor is driven from another pass transistor

Transmission Gate VinVout C C P-type N-type Rp Rn R = Rp // Rn Resistive Model Cp Cn Capacitative Model C = Cp // Cn

Gate (Restoring) Logic Based on general arrangement of inverter NAND gates can be constructed with both CMOS and NMOS technology For NMOS, L:W ratio must be considered to achieve desired Zpu / Zpd ratio What is the required L:W ratio for NMOS NAND gate with N inputs? –Zpu / (n* Zpd ) = 4 / 1 –See derivation in Kamran and Eshraghian pages

NAND Gates NMOS NAND gate requirements larger than those for inverter. Need additional transistors and corresponding adjustment in length of pull- up transistor NMOS NAND gate delays are increased in direct proportion to number of inputs added, Tnand = N*Tinv For CMOS NAND gate natural asymmetry is improved Must allow for extended fall time on capacitative loads due to additional n-transistors in series

NOR Gates NMOS NOR Gates –can be easily extended to large number of inputs –each pd has same ratio as for an inverter –area reasonable since pu not affected by number of inputs –speed as fast as an inverter -> preferred nmos gate CMOS NOR Gates –pull-up resistance effect aggravated by number of transistors connected in series (p-type) -> rise and fall time asymmetries increased –shift in transfer function -> noise immunity decreased –will need L:W ratio adjustments