ECE 3110: Introduction to Digital Systems Chapter 5 Combinational Logic Design Practices Documentation Standards (contd.)

2 Previous… Block diagram Schematics Diagram Gate symbols Signal names Active levels for signal names

3 Active Levels for Pins When we draw the outline of a logic symbol, we think of the given logic function as occurring inside that outline. In logic gates and logic structures the inversion bubble indicates the active level of the signal Examples: - 2-to- 4 Decoder - EN_L is active low - A and B are active high - Y0_L, Y1_L, Y2_L,Y3_L are active low EN A B Y0 Y1 Y2 Y3 EN_L A B Y0_L Y1_L Y2_L Y3_L

4 More ways of obtaining AND/OR functions (Generalized AND/OR function). Four ways of AND function: output is asserted if both of its inputs are asserted.  AND gate (74x08): active-high input/output  NAND gate (74x00): active-high input, active-low output  NOR gate (74x02): active-low input, active-high output  OR gate (74x32): active-low input/output Four ways of OR function: output is asserted if either of its inputs are asserted.  OR gate (74x32): active-high input/output  NOR gate (74x02): active-high input, active -low output  NAND gate(74x00): active-low inputs, active-high output  AND gate (74x08): active-low inputs/output

5 Bubble-to-Bubble Logic Design Purpose : To make it easy to understand the function of the Logic circuit by choosing appropriate logic symbols and signal names including active-level designators. ERROR FAIL_L OVERFLOW_L ERROR FAIL_L OVERFLOW_L

6 Bubble-to-Bubble Logic Design Rules - The active level of the output signal of a logic device should match the active level of the device’s output pin. Active-low if the device symbol has an inversion bubble, active-high if not. - If the active level of an input signal is the same as that of the device’s input pin to which it’s connected, then the logic function inside the symbolic outline is activated when the signal is asserted. Most common case. - If the active level of an input signal is the opposite of that of the input pin to which it’s connected, then the logic function inside the symbolic outline is activated when the signal is negated. Should be avoided. ERROR READY ERROR READY_L REQUEST ENABLE_L REQUEST ENABLE HALT_L ERROR OVERFLOW ERROR FAIL_L OVERFLOW_L

7 Examples (Wakerly pp322)

8 Another example

9 Drawing Layouts Inputs to the left, outputs to the right. Signals flow from left to right. Signal paths should be connected. Broken signal paths should be flagged to indicate the source or destination and direction. Crossing lines/Connected lines (T-type connection) Multiple pages schematics: - Flat Structure. - Hierarchical Structure.

10 Drawing Layout: Flat schematic structure 4,6 5

11 Hierarchical schematic structure

12 Some rules to avoid common errors Use exactly the same name for same signal. Use different names for different signals. (especially cross pages) Use appropriate active levels for signal names Use “T” convention for connected lines.

13 Buses Buses should be named : DATA[0-7], CONTROL A bus name may use brackets and a colon to denote a range Buses are drawn with thicker lines than ordinary signals. Individual signals are put into or pulled out of the bus by connecting an ordinary signal line to the bus and writing the signal name. (A special connection dot is often used.) A signal extracted from a bus should be named Inter-page signal/Bus Flags :  Uni-direction  Bi-direction Example: Figure 5-16, pp327 (next slide) DATA[0-7] DATA5 DATA6

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15 Schematic diagram/Logic Diagram Logic Diagram Schematic Diagram Bubble-to-Bubble Logic IC-Type-Logic Family Pin numbers- Pin Diagram Reference designator- Unit Number A B F A_L B_L F 74LS04 74LS U1 U2

16 Complete schematic diagram IC types: a part number identifying the IC that performs a given logic function. Also defines the device’s logic family and speed. Eg. 74HCT00, 74LS00 Reference designators: a particular instance of that IC type installed in the system. U1,U2… Pin numbers: used to locate individual logic signal numbers on its pins.

17 Example schematic

18 Dual-inline packages (74 series)

19 Pinouts for SSI ICs in standard dual- inline packages (pp. 329) Small elements in 74x03 indicate an open-drain or open-collector output

20 Combinational SSI devices (Contd.) Small elements in 74x14 indicate hysteresis

21 Combinational SSI devices (Contd.) Small elements in 74x266 indicate an open-drain or open-collector output

22 Next… Timing Reading Wakerly CH