EE141 © Digital Integrated Circuits 2nd Combinational Circuits 1 Digital Integrated Circuits A Design Perspective Designing Combinational Logic Circuits Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 2 Combinational vs. Sequential Logic CombinationalSequential Output = f ( In ) Output = f ( In, Previous In )

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 3 Static CMOS Circuit  At every point in time (except during the switching transients) each gate output is connected to either V DD orV ss via a low-resistive path.  The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods).  This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 4 Static Complementary MOS The PUN and PDN are structured in a mutually exclusive fashion such that only one of the them is conducting in steady-state V DD F(In1,In2,…InN) In1 In2 InN In1 In2 InN PUN PDN PMOS only (make a connection from Vdd to F when F(In1,…InN)=1 NMOS only (make a connection from Gnd to F when F(In1,…InN)=0 … …

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 5 Static Complementary CMOS  Functionally, a transistor can be thought of as a switch. PDN is on when input signal is high and off when low. PUN is on when signal is low and off when high.  PDN network is constructed using NMOS while PUN using PMOS. The primary reason for this is that NMOS produce “strong zeros” while PMOS generates “strong ones”, why?

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 6 Threshold Drops V DD V DD  0 PDN 0  V DD CLCL CLCL PUN V DD 0  V DD - V Tn CLCL V DD V DD  |V Tp | CLCL S DS D V GS S SD D That is why PMOS is used in PUN, and NMOS in PDN

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 7 NMOS Transistors in Series/Parallel Connection Transistors can be thought of as a switch controlled by its gate signal NMOS switch closes when switch control input is high NAND NOR X: GND Y: output

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 8 PMOS Transistors in Series/Parallel Connection NOR NAND X: V DD Y: output

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 9 Complementary CMOS Logic Style Number of transistors required to implement an N- input logic gate is 2N

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 10 Example Gate: NAND

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 11 Example Gate: NOR

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 12 Complex CMOS Gate OUT = D + A (B + C) D A BC D A B C

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 13 Constructing a Complex Gate

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 14 OAI22 Logic Graph C AB X = (A+B)(C+D) B A D C D A B C D XOR, XNOR ?

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 15 Properties of Complementary CMOS Gates Snapshot High noise margins: V OH andV OL are atV DD andGND, respectively. No static power consumption: There never exists a direct path betweenV DD and V SS (GND) in steady-state mode. Comparable rise and fall times: (under appropriate sizing conditions)

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 16 Complementary MOS Properties  Full rail-to-rail swing; high noise margins  Logic levels not dependent upon the relative device sizes; ratioless  Always a path to Vdd or Gnd in steady state; low output impedance  Extremely high input resistance; nearly zero steady-state input current  No direct path steady state between power and ground; no static power dissipation  Propagation delay as function of load capacitance and resistance of transistors

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 17 Voltage Transfer Characteristics  Multi-dimensional plot (can be obtained using DC sweep analysis)

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 18 Delay: Switch Delay Model A R eq A RpRp A RpRp A RnRn CLCL A CLCL B RnRn A RpRp B RpRp A RnRn C int B RpRp A RpRp A RnRn B RnRn CLCL NAND2 INV NOR2

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 19 Input Pattern Effects on Delay  Delay is dependent on the pattern of inputs  Low to high transition  both inputs go low –delay is 0.69 R p /2 C L  one input goes low –delay is 0.69 R p C L  High to low transition  both inputs go high –delay is R n C L CLCL B RnRn A RpRp B RpRp A RnRn C int

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 20 Delay Dependence on Input Patterns A=B=1  0 A=1, B=1  0 A=1  0, B=1 time [ps] Voltage [V] Input Data Pattern Delay (psec) A=B=0  1 67 A=1, B=0  1 60 A= 0  1, B=1 64 A=B=1  0 45 A=1, B=1  0 80 A= 1  0, B=1 81 NMOS = 0.5  m/0.25  m PMOS = 0.75  m/0.25  m C L = 100 fF The difference between the later two cases of H-L has to do with the internal node capacitance charging

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 21 Transistor Sizing CLCL B RnRn A RpRp B RpRp A RnRn C int B RpRp A RpRp A RnRn B RnRn CLCL The goal is to size the gate so that it has approximately the same delay (mostly worst-case delay) as an minimum- size inverter (9λ/2λ,3λ/2λ) First-order estimate neglecting velocity saturation effects (smaller for stacked transistor) and self-loading Assumes Rp = Rn

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 22

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 23 Transistor Sizing a Complex CMOS Gate OUT = D + A (B + C) D A BC D A B C Note: the number for PMOS is with respect to PMOS counterpart in minimum size inverter, and NMOS to NMOS counterpart (27λ/2λ) (6λ/2λ)

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 24 Fan-In Considerations DCBA D C B A CLCL C3C3 C2C2 C1C1 Distributed RC model (Elmore delay) t pHL = 0.69 R eqn (C 1 +2C 2 +3C 3 +4C L ) Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case. C 1 ? C 2 ? C 3 ? C L ? C 1 : C dbD, C sbC, 2C gdD, 2C gsC

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 25 The Elmore Delay RC Chain

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 26 t p as a Function of Fan-In for NAND t pLH t p (psec) fan-in Gates with a fan-in greater than 4 should be avoided. t pHL quadratic linear tptp Assumes fixed fan-out

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 27 t p as a Function of Fan-Out t p NOR2 t p (psec) eff. fan-out All gates are scaled using the switched delay model. (why delay of NOR2 and NAND2 still lager?) Intrinsic cap. t p NAND2 t p INV

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 28 t p as a Function of Fan-In and Fan-Out  Fan-in: quadratic due to increasing resistance and capacitance  Fan-out: each additional fan-out gate adds two gate capacitances to C L t p = a 1 FI + a 2 FI 2 + a 3 FO

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 29 Fast Complex Gates: Design Technique 1  Transistor sizing  as long as fan-out capacitance dominates  Progressive sizing (non-uniform sizing) In N CLCL C3C3 C2C2 C1C1 In 1 In 2 In 3 M1 M2 M3 MN Distributed RC line M1 > M2 > M3 > … > MN (the transistor closest to the output is the smallest) Can reduce delay by more than 20%; decreasing gains as technology shrinks (due to layout)

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 30 Fast Complex Gates: Design Technique 2  An input signal is called critical if it is the last signal of all inputs to assume a stable value  The path through the logic which determines the ultimate speed of the structure is called the critical path  Putting the critical path transistors closer to the output of the gate can result in a speed up

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 31 Fast Complex Gates: Design Technique 2  Transistor ordering C2C2 C1C1 In 1 In 2 In 3 M1 M2 M3 CLCL C2C2 C1C1 In 3 In 2 In 1 M1 M2 M3 CLCL critical path charged 1 0101 1 delay determined by time to discharge C L, C 1 and C 2 delay determined by time to discharge C L 1 1 0101 charged discharged

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 32 Fast Complex Gates: Design Technique 3  Alternative logic structures F = ABCDEFGH

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 33 Fast Complex Gates: Design Technique 4  Isolating fan-in from fan-out using buffer insertion (inverter chains) CLCL CLCL

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 34 Sizing Logic Paths for Speed  Frequently, input capacitance of a logic path is constrained  Logic also has to drive some capacitance  Example: ALU load in an Intel’s microprocessor is 0.5pF  How do we size the ALU datapath to achieve maximum speed?  We have already solved this for the inverter chain – can we generalize it for any type of logic?

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 35

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 36 Buffer Example For given N: C i+1 /C i = C i /C i-1 To find N: C i+1 /C i ~ 4 How to generalize this to any logic path? CLCL InOut 12N

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 37 Apply to Inverter Chain CLCL InOut 12N t p = t p1 + t p2 + …+ t pN

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 38 Optimal Tapering for Given N Delay equation has N - 1 unknowns, C gin,2 – C gin,N Minimize the delay, find N - 1 partial derivatives Result: C gin,j+1 /C gin,j = C gin,j /C gin,j-1 Size of each stage is the geometric mean of two neighbors - each stage has the same effective fanout (C out /C in ) - each stage has the same delay

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 39 Optimum Delay and Number of Stages When each stage is sized by f and has same eff. fanout f: Minimum path delay Effective fanout of each stage:

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 40 Generalized logic path How to size this generalized logic path?

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 41 Logical Effort Logical effort is the ratio of input capacitance of a gate to the input capacitance of an minimum-size inverter gate with the same output current (considering worst case) g = 1 g = 4/3 g = 5/3

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 42 Normalizing the delay to inverter Now, consider to normalize everything to an minimum-size inverter (Assume  = 1). Then, (1) What is the load capacitance in each case for an effective fan-out of 2 (with respect to one input) for example? (2) What is the intrinsic delay in each case? (3) what is the external delay?

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 43 Delay in a logic gate with minimum size So, if we normalize everything to an minimum-size inverter with g inv =1, p inv = 1 (everything is measured in unit delays  inv And assume  = 1 Then we can introduce p – intrinsic delay factor g – logical effort f – effective fanout

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 44 Logical effort Gate delay: d = h + p effort delay intrinsic delay Effort delay: h = g f logical effort effective fanout (of each stage) = C out /C in Effective fanout (electrical effort) is a function of load/gate size

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 45 Logical Effort  Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates  Logical effort represents the fact that for a given load, complex gate has to work harder (in terms of transistor sizes) than an inverter to get a similar delay).  In another way, complex gives more loading capacitance to the previous gate when made comparable to inverter after sizing  How much harder? How to measure it?  Logical effort for a complex gate can be computed from the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current (Logical effort is a function of topology, independent of sizing)  Logical effort increases with the gate complexity

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 46 Logical Effort Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann, 1999.

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 47 Logical Effort of Gates Fan-out (h) Normalized delay (d) t pINV t pNAND F(Fan-in) g = p = d = g = p = d =

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 48 Logical Effort of Gates Fan-out (h) Normalized delay (d) t pINV t pNAND F(Fan-in) g = 1 p = 1 d = f+1 g = 4/3 p = 2 d = (4/3)f+2 Intrinsic delay is increased by twice since the intrinsic capacitance gets two times larger

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 49 Logical Effort of Gates