F = ABD + ABD + ABD + BCD _ __ _ _ Another thing about Karnaugh Maps… 1 A D C 0 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 1110 1001 0000 1110 B The two blue.

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Presentation transcript:

F = ABD + ABD + ABD + BCD _ __ _ _ Another thing about Karnaugh Maps… 1 A D C B The two blue lines are logically adjacent to each other. So are the two red lines. So, when grouping the 1s…

F = ABD + ABD + ABD + BCD _ __ _ _ Let’s check our work… 2 A D C B ABCDABCDFABCDABCDF ABD BCD ____ _ _ _ _ _ _ _ _

Logic Gates 3

4

Example Using AND, OR, and INVERTER gates, implement F = AB + CD + BCD. _ Start with the 4 inputs A, B, C, and D. Use an inverter to create D. AND together the necessary terms to obtain each of the three terms of F, then OR the three terms together. _

A little practical insight… 6 NAND and NOR gates are preferred to AND and OR gates for several reasons (simpler circuitry, faster operation, etc.). Can you implement the last example using only NAND and NOR gates? XY ___ XY1 NAND ___

A little practical insight… 7 NAND and NOR gates are preferred to AND and OR gates for several reasons (simpler circuitry, faster operation, etc.). Can you implement the last example using only NAND and NOR gates? G27 2 – 7400Quad 2-input NAND 1 – 7420Dual 4-input NAND 1 – 741G27Single 3-input NOR

A little practical insight… 8 2-input NAND TTL circuit (Transistor-Transistor Logic)

A little practical insight… 9 Logic FamilySwitchingPower perYear (Technology)Speed (MHz)Gate (mW)Introduced RTL (Resistor Transistor Logic) DTL (Diode- varies Transistor Logic) CMOS up to (Complementary Metal-Oxide Semiconductor) TTL (Transistor- typically Transistor Logic) (up to GHz) ECL (Emitter Coupled Logic) Apollo Guidance Computer