Chapter 3 Basic Logic Gates William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Introduction to Logic Gates Basic building block for digital circuitry Has only 1 output, but 1 or more inputs Output will be either a 1 or 0 Combine gates to create electronic systems 5 basic logic gates –AND –OR –NOT (inverter) –NAND –NOR

The AND Gate The output, X, is HIGH if input A AND input B are both HIGH Boolean Equation X = A AND B or X = AB Can have more than two inputs Number of combinations = 2 N where N is the number of inputs

Figure 3-1 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. AND Gate Boolean Equation: X = A AND B or X = AB

William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Number of combinations = 2 N where N = number of inputs

Figure 3–2 AND gate used to activate a burglar alarm. William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–3 Electrical analogy for an AND gate: (a) using manual switches; (b) using transistor switches. William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–4 Multiple-input AND gate symbols. William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Table 3–2 Truth Table for a Four-Input AND Gate William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

The OR Gate The output at X will be HIGH whenever input A or input B is HIGH or both are HIGH Can have more than two inputs Boolean Equation X = A OR B or X=A + B William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3-5 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–6 Electrical analogy for an OR gate: (a) using manual switches; (b) using transistor switches. William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–6 (continued) Electrical analogy for an OR gate: (a) using manual switches; (b) using transistor switches. William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–7 Three-input OR gate symbol. Figure 3–8 Eight-input OR gate symbol.

Table 3–4 Truth Table for a Three-Input OR Gate William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Timing Analysis Timing Diagram –Illustrates graphically how the output levels change in response to changes to the inputs Oscilloscope –voltage versus time –up to four –ideal for comparing one waveform to another Logic Analyzer –voltage versus time –state table –up to 16

Figure 3–10 Timing analysis of an AND gate: (a) waveform sketch; (b) actual logic analyzer display. William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Enable and Disable Functions Enable –turn ON –see Figure 3-17 Disable –turn OFF –see Figure 3-18 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–17 Using an AND gate to enable/disable a clock oscillator. William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–18 Using an OR gate to enable/disable a clock oscillator. William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Using Integrated Circuit Logic Gates 4 examples –7408 (74HC08) quad 2-input AND gate –7411 (74HC11) triple 3-input AND gate –7421 (74HC21) dual 4-input AND gate –7432 (74HC32) quad 2-input OR gate Dual inline packages (DIP)

Figure 3–19 The 7408 quad two-input AND gate IC pin configuration. William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3-20 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–21 Pin configurations for other popular TTL and CMOS AND and OR gate ICs: (a) 7411 (74HC11); (b) 7421 (74HC21); (c) 7432 (74HC32). William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

The Inverter Used to complement or invert a digital signal NOT gate Only 1 input and 1 output If input is HIGH, output will be LOW If input is LOW, output will be HIGH Boolean Equation –X = NOT A –X = A

Figure 3-27 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–28 Timing analysis of an inverter gate: (a) waveform sketch; (b) oscilloscope display. William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

The NAND Gate Same as the AND gate except that its output is inverted Boolean Equation –X = NOT A AND B –X = AB multiple inputs - the output is always HIGH unless all inputs go HIGH

Figure 3-29 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–30 AND–INVERT equivalent of a NAND gate with A = 1, B = 1. William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–31 Symbols for three- and eight-input NAND gates. William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Table 3–7 Truth Table for a Three-Input NAND Gate William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

The NOR Gate Same as the OR gate except that its output is inverted Boolean Equation –X = NOT A + B –X = A + B The output is always LOW unless all the inputs are LOW

Figure 3-36 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

InputNot AANDORNANDNOR ABAABA+BABA+B

Logic Gate Waveform Generation Repetitive waveform Waveform generator –Johnson shift counter William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–44 Generating a 3-ms HIGH pulse using an AND gate and a Johnson shift counter. William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Using Integrated-Circuit Logic Gates Hex - six gates Quad - four gates Three-, four-, and eight-input configurations William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3-60 Figure 3-61 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3-65 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Introduction to Troubleshooting Techniques The procedure used to find the fault in a circuit. Logic Probe has a metal tip and indicator lamp(s) Floating - open circuit, neither HIGH nor LOW

Troubleshooting Techniques (cont’d) Logic Pulser –provides digital signal to a circuit –By applying a pulse and observing the output, you can tell if the pulse signal is getting through Voltmeter –Can be used in place of a logic probe to determine output –Approximately 5 volts – HIGH (1) –Approximately 0 volts – LOW (0) –In between - Floating

Figure 3–23 Four common printed-circuit faults: (a) misalignment of pin 14; (b) cracked board William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–23 (continued) Four common printed-circuit faults: (c) solder bridge; (d) burned transistor. William Kleitz Digital Electronics with VHDL, Quartus ® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Summary The AND gate requires that all inputs are HIGH in order to get a HIGH output The OR gate outputs a HIGH if any of its inputs are HIGH An effective way to measure the precise timing relationships of digital waveforms is with an oscilloscope or a logic analyzer William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Summary Beside providing the basic logic functions, AND and OR gates can also be used to enable or disable a signal to pass from one point to another There are several integrated circuits available in both TTL and CMOS that provide the basic logic functions William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Summary Two important troubleshooting tools are the logic pulser and the logic probe. The pulser is used to inject pulses into a circuit under test. The probe reads the level at a point in a circuit to determine is it is HIGH, LOW, or floating An inverter provides an output that is the complement of its input William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Summary A NAND gate outputs a LOW when all of its inputs are HIGH A NOR gate outputs a HIGH when all of its inputs are LOW Specialized waveforms can be created by using a repetitive waveform generator and the basic gates William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Summary Manufacturer’s data manuals are used by the technician to find the pin configuration and operating characteristics for the ICs used in modern circuitry. William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.