Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-1 Lectures 16 Transfer Characteristics (Delay and Power) Feb. 10, 2003

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-2 Topics n Electrical properties of static combinational gates: –Noise margin and transfer curve; –delay; –power.

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-3 Delay n Assume ideal input (step), RC load.

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-4 Delay assumptions n Assume that only one transistor is on at a time. This gives two cases: –rise time, pullup on; –fall time, pullup off. n Assume resistor model for transistor. Ignores saturation region and mischaracterizes linear region, but results are acceptable.

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-5 Current through transistor n Transistor starts in saturation region, then moves to linear region.

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-6 Resistive model for transistor n Average V/I at two voltages: –maximum output voltage –middle of linear region n Voltage is V ds, current is given I d at that drain voltage. Step input means that V gs = V DD always.

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-7 Resistive approximation

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-8 Ways of measuring gate delay n Delay: time required for gate’s output to reach 50% of final value. n Transition time: time required for gate’s output to reach 10% (logic 0) or 90% (logic 1) of final value.

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-9 Inverter delay circuit n Load is resistor + capacitor, driver is resistor.

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-10 Inverter delay with  model  model: gate delay based on RC time constant . n V out (t) = V DD exp{-t/(R n +R L )/ C L} n t f = 2.2 R C L n For pullup time, use pullup resistance.

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-11  model inverter delay n 0.5 micron process: –R n = 3.9 k  –C l = 0.68 fF n So –t d = 0.69 x 3.9 x.68E-15 = 1.8 ps. –t f = 2.2 x 3.9 x.68E-15 = 5.8 ps.

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-12 Example 2 n Delay

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-13 Power consumption analysis n Almost all power consumption comes from switching behavior. n Static power dissipation comes from leakage currents. n Surprising result: power consumption is independent of the sizes of the pullups and pulldowns.

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-14 Other models n Current source model (used in power/delay studies): –t f = C L (V DD -V SS )/I d – = C L (V DD -V SS )/0.5 k’ (W/L) (V DD -V SS -V t ) 2 n Fitted model: fit curve to measured circuit characteristics.

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-15 Power consumption n A single cycle requires one charge and one discharge of capacitor: E = C L (V DD - V SS ) 2. n Clock frequency f = 1/t. n Energy E = C L (V DD - V SS ) 2. n Power = E x f = f C L (V DD - V SS ) 2.

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-16 Observations on power consumption n Resistance of pullup/pulldown drops out of energy calculation. n Power consumption depends on operating frequency. –Slower-running circuits use less power (but not less energy to perform the same computation).

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-17 Example 3 n Power

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-18 Lectures 17 VHDL Feb. 12, 2003

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-19 Basic VHDL Copyright  RASSP E&F All rights reserved. This information is copyrighted by the RASSP E&F Program and may only be used for non-commercial educational purposes. Any other use of this information without the express written permission of the RASSP E&F Program is prohibited. All information contained herein may be duplicated for non- commercial educational use provided this copyright notice is included. No warranty of any kind is provided or implied, nor is any liability accepted regardless of use. FEEDBACK: The RASSP E&F Program welcomes and encourages any feedback that you may have including any changes that you may make to improve or update the material. You can contact us at or

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-20 Topics n Introduction n VHDL Design Example n Synthesis and VHDL

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-21 Reasons for Using VHDL n VHDL is an international IEEE standard specification language (IEEE ) for describing digital hardware used by industry worldwide –VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language n VHDL enables hardware modeling from the gate to system level n VHDL provides a mechanism for digital design and reusable design documentation

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-22 Gajski and Kuhn’s Y Chart Physical/Geometry Structural Behavioral Processor Hardware Modules ALUs, Registers Gates, FFs Transistors Systems Algorithms Register Transfer Logic Transfer Functions Architectural Algorithmic Functional Block Logic Circuit Rectangles Cell, Module Plans Floor Plans Clusters Physical Partitions

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-23 Putting It All Together GenericsPorts Entity Architectur e Concurren t Statement s Process Sequential Statements Concurren t Statement s Package

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-24 VHDL Design Example n Problem: Design a single bit half adder with carry and enable n Specifications –Inputs and outputs are each one bit –When enable is high, result gets x plus y –When enable is high, carry gets any carry of x plus y –Outputs are zero when enable input is low x y enable carry result Half Adder

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-25 VHDL Design Example Entity Declaration n As a first step, the entity declaration describes the interface of the component –input and output ports are declared x y enable carry result Half Adder ENTITY half_adder IS PORT( x, y, enable: IN BIT; carry, result: OUT BIT); END half_adder;

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-26 VHDL Design Example Behavioral Specification n A high level description can be used to describe the function of the adder l The model can then be simulated to verify correct functionality of the component ARCHITECTURE half_adder_a OF half_adder IS BEGIN PROCESS (x, y, enable) BEGIN IF enable = ‘1’ THEN result <= x XOR y; carry <= x AND y; ELSE carry <= ‘0’; result <= ‘0’; END IF; END PROCESS; END half_adder_a;

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-27 VHDL Design Example Data Flow Specification n A second method is to use logic equations to develop a data flow description l Again, the model can be simulated at this level to confirm the logic equations ARCHITECTURE half_adder_b OF half_adder IS BEGIN carry <= enable AND (x AND y); result <= enable AND (x XOR y); END half_adder_b;

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-28 VHDL Design Example Structural Specification n As a third method, a structural description can be created from predescribed components l These gates can be pulled from a library of parts x y enable carry result

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-29 VHDL Design Example Structural Specification (Cont.) ARCHITECTURE half_adder_c OF half_adder IS COMPONENT and2 PORT (in0, in1 : IN BIT; out0 : OUT BIT); END COMPONENT; COMPONENT and3 PORT (in0, in1, in2 : IN BIT; out0 : OUT BIT); END COMPONENT; COMPONENT xor2 PORT (in0, in1 : IN BIT; out0 : OUT BIT); END COMPONENT; FOR ALL : and2 USE ENTITY gate_lib.and2_Nty(and2_a); FOR ALL : and3 USE ENTITY gate_lib.and3_Nty(and3_a); FOR ALL : xor2 USE ENTITY gate_lib.xor2_Nty(xor2_a); -- description is continued on next slide

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-30 VHDL Design Example Structural Specification (cont.) -- continuing half_adder_c description SIGNAL xor_res : BIT; -- internal signal -- Note that other signals are already declared in entity BEGIN A0 : and2 PORT MAP (enable, xor_res, result); A1 : and3 PORT MAP (x, y, enable, carry); X0 : xor2 PORT MAP (x, y, xor_res); END half_adder_c;

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-31 Synthesis and VHDL n Logic synthesis n Rewrite the half-adder to synthesized VHDL –Library –Std_logic and std_logic_vector

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-32 Full Adder Example

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-33 Lectures 18 Synopsys Tutorial Feb. 14, 2003

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-34 Synopsys and VHDL u Lab 2

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-35

Modern VLSI Design 3e: Chapters 3 & 8Partly from 2002 Prentice Hall PTR week6-36