Elec 関係、情報収集 ( 中。。 )

Design review for NSW electronics (2015/2) Design review for NSW ASIC (2015/4) NSW elec Wiki Documents Meeting NSW Electronics (Friday, Lorne) NSW Trigger Processor WG (??, Joao)

Trigger Readout Backend Frontend VMM, TDS, ART, ROC Are ASICs (IBM 130nm)

L1DDC board Based on commercial FPGA First prototype being tested ART ASIC -Trigger for MM -First prototype delivered and under test ART board prototype being tested Interface with the sector logic fully defined Work using commercial FPGAs. Two hardware options for the trigger processor ATCA carrier and mezzanines are currently under evaluation VMM2 started and still on going VMM3 will be submit end of July 2015 MMFE8 (8 VMM chips) : emerging for MM. design phase for sTGC Mini2 : 2 VMM2 boards; version 2 is being produced

ADDC Prototype by BNL L1DDC Prototype by NTU?

MMFE-8 VMM2-1 VMM2-2 VMM2-3VMM2-4VMM2-5VMM2-7VMM2-6VMM2-8 FPGA PHY ENET RJ45 Power Input HDMI x2 JTAG miniSAS L1DDC (Bottom) Zebra Input 2Zebra Input 1 miniSAS ADDC (Bottom) DCDC-1 DCDC-2 DCDC-3 DCDC-4 Input Protecti on Test Connect or Clocks & FLASH FPGA Power Analog Power Distribution Serial Num ber VMM chip - 64channels Readout output Trigger output

   NSW trigger concept Phase I upgrade: Increased backgrounds, but must maintain existing trigger rate Filter “Big Wheel” muon candidates to remove tracks that are not from the IP Only track “A” should be a trigger candidate: pointing:  <  7.5mrad Challenge is latency: 500nsec for electronics + 500ns fibres to be in time for Big Wheel Micromegas: 2M strips, 0.4mm sTGC: 280K strips (3.2mm), 45K pads, 28K wires sTGC, MM find candidates independently, list merged for Sector Logic Hit per layer: sTGC: hit is centroid of 3-5 strips Micromegas: hit is address of strip

Finds candidates in R-  tagged by p T Mismatch of NSW and BW detector boundaries  fan-out to several modules Big Wheel Regions-of-Interest to be confirmed by NSW. Red lines are NSW sector boundaries. Sector Logic

sTGC strips: one output per channel 6-bit flash ADC of strip signal peak  charge; serial output at 160Mb/s Centroid of 3 to 5 3.2mm strips gives track coordinate in a layer sTGC pads: one output per channel 10nsec pulse at peak, or use leading edge of Time-over- Threshold Coincidence in 8-layer tower of pads chooses which strips to transfer to centroid finder Front end outputs for trigger path Lorne Levinson, Overview of NSW trigger electronics 16NSW Electronics Design Reviews, February 2015 Micromegas: one output per 64-channel chip Address in Real Time (ART) of first (in time) strip hit in each BC per chip Address of the 0.4mm strip gives track coordinate “  TPC” mode probably 1 st

sTCGsTCG sTCGsTCG sTCGsTCG sTCGsTCG sTCGsTCG sTCGsTCG sTCGsTCG sTCGsTCG sTGC trigger scheme 17 On-chamber ASICS On Rim of NSW FPGAs USA 15 Pad Trigger Strip TDS Strip TDS Pad TDS Pad TDS Pad VMM Pad VMM sTGC Trigger Processor sTGC Trigger Processor Strip VMM Strip VMM sTCGsTCG sTCGsTCG sTCGsTCG sTCGsTCG sTCGsTCG sTCGsTCG sTCGsTCG sTCGsTCG Strip VMM Strip VMM 9 Pad trigger uses pad tower coincidence to choose ONLY the relevant band of strips. Physical pads staggered by ½ pad in both directions Logical pad-tower defined by projecting from 8 layers of staggered pad boundaries Pad-tower coincidence = 2  3-out-4 overlapping pads Router 1/16 th sector Problem: no BW to read all strips Strip TDS Strip TDS Only one Strip TDS chosen Lorne Levinson, Overview of NSW trigger electronics NSW Electronics Design Reviews, February 2015

sTCGsTCG sTCGsTCG sTCGsTCG sTCGsTCG sTCGsTCG sTCGsTCG sTCGsTCG sTCGsTCG Micromegas trigger scheme 18 On-chamber ASICS USA 15 ART VMM Strip VMM Strip MM Trigger Processor MM Trigger Processor VMM Strip VMM Strip sTCGsTCG sTCGsTCG sTCGsTCG sTCGsTCG sTCGsTCG sTCGsTCG MIcRomegasMIcRomegas MIcRomegasMIcRomegas VMM Strip VMM Strip Each VMMs send address of its first hit in each BC to an ART ASIC. 64 channels = 2.6cm Use the coordinate of the center of the strip for the slope calculation ART chooses up to 8 addresses from 32 VMMs to send Less accurate than sTGC centroid Simpler architecture Plan to use GBT for transmission 1/16 th sector

Trigger Processor One sTGC and one MM Trigger Processor per 1/16 th sector Large Xilinx FPGA; ATCA in USA15 (radiation protected area) Receives 32 fibres (90m) from ART ASICs or 32 (was 24) fibres from Router sTGC: centroid finder; MM uses ART address as hit Find valid track segments that can corroborate hits in the Big Wheel Combine list from MM and sTGC, removing duplicates Send valid segments to Sector Logic for matching to the Big Wheel hits. Up to 8 per BC Input and output data read out to ATLAS on Level-1 Accept Monitoring and diagnostic data sent to a monitor PC

Trigger processor platform LAr SRS ATCA-based FPGA boards, one board per octant, 2 crates Two MM & two sTGC sectors per carrier One sTGC or one MM sector per FPGA Input fibers per sector: MM: 32, sTGC: 32 Transfer candidates between MM & sTGC FPGAs via low latency lines Avoid development of yet-another-ATCA-FPGA board Two candidate carriers & mezz’s: LAr, SRS SRS: two FPGAs per mezz ×2 36 input, 36 output fibres LAr: one FPGA per AMC mezz ×4 48 input, 48 output fibres

MM Latency min (ns) max (ns) Notes TOF from interaction point to MM (z=7.744 m)30.2 To periphery of + 5 cm IP Earliest arrival hit5075Depends onsite of rolling window (2 or 3 BC) VMM2 chip latency1015ART at threshold crossing instead of peak FEB to Trigger Driver cable33Twin-ax cable ns/m Trigger driver latency41 ART encoding (companion chip): from VMM to until first data bunch is output to GBT Uplink GBT latency (Tx)99111GBTx measured Mar 2014 Fiber to Trigger Processor card in USA15 (80-90 m) ns/m (fiber length might be reduceable) Uplink GBT latency (Rx)44 GBT-FPGA (optimized) - includes GTX-TX (Kai Chen) Trigger Algorithm MHz clock Re-synch to 320 MHz clock driving output serializer ° phase chosen to best match pipeline length Output to Sector Logic serializer (Tx only)2530Deserializer on Sector Logic latency budget Fiber to Sector Logic m 5ns/m Total763869TDR was ns

sTGC Latency min (ns) max (ns) Notes TOF from interaction point to NSW (z=7.8 m) 2931 To periphery of Pad signal jitter in chamber 510 Worst case due to tracks midway between wires (late signals due to long drift time) Pad ASD (VMM) 4050 ASD latency + time-to-peak Serialize 32 Gbps 1620 TDS to pad triger on rim, max 4 m 1823 Twin-ax cable delta R = 3-4 m + delta Z = ns/m Deserialize 32 pads 3040 On Pad Trigger Pad trigger (incl deskew) 1525 Strips are pipelined until pad trigger arrives Serializer of Pad Trigger output ns for Gbits/sec (simultaneous with deserializer) Pad trigger to on-chamber TDS ASIC 1823 Twin-ax cable delta R = 3-4 m + delta Z = ns/m TDS: Trigger Data Serializer 95 (Strip data transferred while waiting for pad trigger) On chamber cabling (up to 3-4m) to Router 1823 Twin-ax cable delta R = 3-4 m + delta Z = ns/m Router 8595 Include deserialization, switch (10 ns), serialization Fiber to Centroid card in USA15 (80-90) ns/m (fiber length might be reduceable) Trigger processor input deserializer 40 sTGC trigger algorithm 56 8 layers done in parallel, measured to be 13 clocks + 5 estimated Re-synch to 320 MHz clock driving output serializer ° phase chosen to best match pipeline length Centroid to Sector Logic serializer (Tx only) 2530 Deserializer on Sector Logic latency budget Fiber to Sector Logic 510 Total TDR was ns

6.7 cm MicroMegas Layers Multilayer 18.5 cm X planeU planeV plane Interaction Point z Strip #S2 Strip #S1 X0X0 X1X1 X2X2 X3X3 U V Slope X 0 = LookUpTable (#S2 - #S1) Local straight track selection based on strip number difference with strip precision Layer Pair Slope Average rms=1.7 mrad Theta Resolution at the entrance of the Muon System Local segment slopes calculation between hits of Layers belonging to the same Layer Pair over 3 BCs. Layer Pair X0X0 X1X1 X2X2 X3X3 UV Matching slope = track candidate Micromegas trigger algorithm I

Implementation for 2048 strips x 8 Layers

Micromegas trigger algorithm II θ Projective “global” slope easy to estimate from slope road Local slope easily calculated through local fit “Global” stereo slope calculated to determine ROI in φ 37 ns latency Arrival of the last hit on the GBT linkCoincidence candidate formed Global horizontal/stereo slopes calculated Local slope calculated ROI determined Projective roads help: create coincidences quickly, reject background from the start

Algorithm efficiency essentially 100% Inefficiencies related to hits with late raise times, detector gaps, low-ionization hits Inefficiencies caused by simulated incoherent backgrounds are small Irreducible inefficiencies due to muon 1 TeV at 5% from showering Algorithm intrinsic resolution of measurement of θ - θ is 1.33mrad but affected by multiple scattering in the calorimeter Performance summary -- Performance summary -- algorithm II

L=7x10^34 <640Mb/s 4~9strip / hit 3BCs