© 2008, Renesas Technology America, Inc., All Rights Reserved 1 Course Introduction Purpose This module provides an overview of sophisticated peripheral functions provided by the MCUs in the M32C series, devices at the top end of the M16C family. Objectives  Gain a basic understanding of the features and operation of the Intelligent I/O peripheral.  Understand the benefits the X-Y Converter provides.  Discover how the DMAC II peripheral operates.  Learn about the CAN peripheral Content 26 pages 4 questions Learning Time 40 minutes

© 2008, Renesas Technology America, Inc., All Rights Reserved 2 Intelligent I/O Peripheral Multi-functional I/O port with many capabilities:  Time measurement  Waveform generation  Clock-synchronous serial I/O  Clock-asynchronous serial I/O (UART)  IEBus* communications  HDLC data processing  and more Consists of four circuit groups, each of which has the following:  One 16-bit free-running timer  Eight 16-bit registers  Two 8-bit shift registers (or one 16-bit register) * IEBus is a trademark of NEC Corporation

© 2008, Renesas Technology America, Inc., All Rights Reserved 3 Functions Available, by Group Time Measurement 1 Intelligent I/O Function Group 0Group 1Group 2Group 3 Groups 0, 1 cascaded 8 channels (3 channels) 2 4 channels (2 channels) 8 channels (3 channels) 8 channels (3 channels) 4 channels (2 channels) 8 channels (3 channels) Digital Filter Trigger Input Pre-scaler Trigger Input Gate 2 channels Not Available Not Available 4 channels (2 channels) 8 channels (3 channels) 8 channels (3 channels) Digital Filter Waveform Generation 1 Single Phase Waveform Output Phase Delayed Waveform Output 8 channels (3 channels) 8 channels (2 channels) SR Waveform Output Available Bit Modulation PWM Output RTP Output Parallel PWM Output Not Available Not Available Not Available Communication 1 Clock Sync Serial I/O Mode UART Mode HDLC Data Processing Mode IE Mode 8 bits, fixedVariable8 bits/16 bits Not Available Available Not Available Not Available Not Available Not Available 1) Time Measurement Function shares pins with the Waveform Generation function 2) Channels for the 100-pin Package are shown in parentheses.

© 2008, Renesas Technology America, Inc., All Rights Reserved 4 Time Measurement Function  Time measurement –The time between every edge (rising, falling or both) is measured.  Digital filter function –The Digital filter samples an input signal every f 1 of f BTi pulses. (Base Counter) –An edge is excepted/counted if the input pulse >3 (<3.5) Base Counter pulses.  Cascaded connection function –Groups 0 and 1 are connected to operate as a 32-bit timer.  Pre-scaler function (Channels 6 and 7) –The time period measured is the time taken for [‘x’+1] edges, where “x” is defined in the Timer Prescaler Register.  Gate function (Channels 6 and 7) –Input signals are only accepted when the “Gate” is enabled. (“Gate” is software controlled.)

© 2008, Renesas Technology America, Inc., All Rights Reserved 5 Time Measurement Examples H’FFFF n p m H’0 pnm INPCij Input Pin GiTMj Register Time Measurement Function— Rising Edge Selected as Trigger nmz H’FFFF n p m H’0 m INPCij Input Pin GiTMj Register Time Measurement Function— Both Edges Selected as Trigger xyp x y z Input Pin nm Gate Control Gate Function Gate Control is not Enabled. Therefore this input is ignored. H’0 n m H’FFFF GiTMj Register

© 2008, Renesas Technology America, Inc., All Rights Reserved 6 Waveform Generation Function Waveforms are generated when the value of the base timer matches the value of the GiPOj registers. (i = 0 to 3, j = 0 to 7) Six output modes are available:  Single-Phase Waveform (supported by Groups 0, 1, 2, 3)  Phase-Delayed Waveform (supported by Groups 0, 1, 2, 3)  Set/Reset Waveform (supported by Groups 0, 1, 2, 3)  Bit-Modulation PWM (supported by Groups 2 and 3)  Real-Time Port (supported by Groups 2 and 3)  Parallel Real-Time Port (supported by Groups 2 and 3)

© 2008, Renesas Technology America, Inc., All Rights Reserved 7 Waveform Generation Examples H’FFFF n m + 2 H’0 Waveform Generation Function— Single-Phase Waveform Output OUTCik pin H’FFFF n m + 2 H’0 Waveform Generation Function— Phase-Delayed Waveform Output OUTCik pin H’FFFF n p + 2 H’0 Waveform Generation Function— Set-Reset Waveform Output OUTCik pin m

© 2008, Renesas Technology America, Inc., All Rights Reserved 8 Bit-Modulation PWM Mode Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Bit 9Bit 8Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 T = 1024 Pulses 64/f n = 0 to 63 n m = 0 to Specifies which PWM pulse is modified Width of LOW / HIGH period is modified by 1 clock Value of ‘m’Pulse to which Bit Time will be added : None t 512 t 256, t 768 t 128,t 384, t 640, t 896 t 64, t 192, t 320, t 448, t 576, t 704, t 832, t 960 : t 1, t 3, t 5, t 7,..… t 1019, t 1021, t 1023 GIPOj Register

© 2008, Renesas Technology America, Inc., All Rights Reserved 9 Communication Function Communication capabilities vary from group to group within the Intelligent I/O peripheral: Groups 0 and 1 support  8-bit Synchronous Serial I/O  8-bit Asynchronous Serial I/O  High-Level Data-Link Control (HDLC) data processing, including bit stuffing, flag detection, abort detection and CRC processing Group 2 supports  Variable Clock Synchronous Serial I/O  IEBus Group 3 supports  8-bit Clock Synchronous Serial I/O  16-bit Clock Synchronous Serial I/O

© 2008, Renesas Technology America, Inc., All Rights Reserved 11 X-Y Conversion Function Converts a 16 x 16 matrix of data by 90 degrees, and inverts high-order and low-order bits After the conversion process, these bits effectively remain stationary. Bit positions after 90 O rotation and high-order to low-order inversion BeforeAfter X0 Register X1 Register X2 Register X3 Register X4 Register X5 Register X6 Register X7 Register X8 Register X9 Register X10 Register X11 Register X12 Register X13 Register X14 Register X15 Register Y0 Register Y1 Register Y2 Register Y3 Register Y4 Register Y5 Register Y6 Register Y7 Register Y8 Register Y9 Register Y10 Register Y11 Register Y12 Register Y13 Register Y14 Register Y15 Register WRITE TO Xn Registers READ FROM Yn Registers CONVERSION

© 2008, Renesas Technology America, Inc., All Rights Reserved 12 DMAC II Request Transfer Data Transfer Block Transfer Space Transfer Direction Transfer Mode Chained Transfer Function Interrupt At End Of Transfer Multiple Transfer Function Item Specification Interrupt request from all peripheral functions if the Interrupt Priority of the interrupt is set to level 7 Memory  Memory (Memory to Memory Transfer) Immediate Data  Memory (Immediate Data Transfer) Memory ( or Immediate Data ) + Memory  Memory (Arithmetic Transfer) 8 bits or 16 bits 64 KByte space; addresses H’0000 to H’FFFF Fixed or Incrementing; can be specified for the Source or Destination address Single or Burst transfer When the preceding transfer has completed its specified number of transfers (counter=0), then the DMAC II automatically begins next set of transfers. Interrupt is generated when transfer count reaches 0 A single Interrupt request causes multiple DMAC II transfers DMAC II Function Transfers performed:  Memory to Memory ( Memory to Memory Transfer )  Immediate Data to Memory( Immediate Data Transfer )  Memory ( or Immediate Data ) + Memory to Memory ( Arithmetic Transfer )

© 2008, Renesas Technology America, Inc., All Rights Reserved 13 Configuring the DMAC II Base Address RAM Base Address Transfer Mode(MOD) Transfer Counter(COUNT) Transfer Source Address (or immediate Data)(SADR) Operation Address 1 (OADR) Transfer Destination Address(DADR) Chained Transfer Address 2 (CADR0) Chained Transfer Address 2 (CADR1) End of Transfer Interrupt Address 3 (IADR0) End of Transfer Interrupt Address 3 (IADR1) 1. Data required only when using Arithmetic Transfer function 2. Data required only when using Chained Transfer function 3. Data required only when using End-of-Transfer interrupt 16-bit registers Required data when performing Memory to Memory, Immediate, and Arithmetic Transfers Required data when performing Multiple Transfers Transfer Mode(MOD) Transfer Counter(COUNT) Transfer Source Address ( or immediate Data )(SADR1) Transfer Destination Address(DADR2) Transfer Source Address ( or immediate Data )(SADR7) Transfer Destination Address(DADR7) Data Format for Chained Transfer Addr, transfer 2 Transfer 2 Address Addr, transfer 3 Interrupt Vector Table

© 2008, Renesas Technology America, Inc., All Rights Reserved 15 Controller Area Network Function Implements a high-integrity, asynchronous, serial data communication bus for automotive and industrial applications FullCAN module — fully compatible with Version 2.0B of the Bosch Specification Features include:  16 slots/message buffers/mailboxes  Acceptance filter masks - One for mailboxes 0 to 13 - One each for mailboxes 14 and 15  1Mbps maximum baud rate  Remote-frame automatic answering function  Time-stamp function  BasicCAN function by using mailboxes 14 and 15  Transmit abort  Loop-back  Error-clearing mode

© 2008, Renesas Technology America, Inc., All Rights Reserved 16 C0SLOT1_0 to 15 Register CAN Implementation CAN Protocol Controller, Version 2.0B C0SLPR Register C0BRP Register C0CTLR0,1 Register C0CONR Register C0IDR Register C0MCTRL0 to 15 Register C0GMR0 to 4 Register C0LMAR0 to 4 Register C0LMBR0 to 4 Register C0EIMKR Register C0EISTR Register C0SIMKR Register C0SLOT0_0 to 15 Register C0AFS Register C0STR Register C0TEC Register C0REC Register Interrupt Control Circuit Acceptance Filter 16-bit timer C0STR Register Message Mailbox 0 to 15 C0SIMKR Register f1 Interrupt Request DATA BUS CAN TX CAN RX

© 2008, Renesas Technology America, Inc., All Rights Reserved 17 CAN0 Control Registers CAN0 Control Register 0 (C0CTRL0)  Reset CAN module via bits RESET0 and RESET1  Loop-back mode  BasicCAN / FullCAN  Time-stamp functionality - Prescaler - Counter Reset  Forced clearing of REC / TEC CAN0 Control Register 1 (C0CTRL1)  CAN0 bank-select switch - Switches between Global Mask register Message-Slot Control register

© 2008, Renesas Technology America, Inc., All Rights Reserved 18 Sleep, Status, ID Registers CAN0 Sleep Control Register  Enters and Exits CAN Sleep Mode CAN0 Status Register  Read-only register; shows the status of the CAN peripheral CAN0 Extended ID Register  16-bit register; specifies whether a mailbox will have a standard 11-bit identifier, or an extended 29-bit identifier

© 2008, Renesas Technology America, Inc., All Rights Reserved 20 CAN0 Configuration Register Controls the timing parameters of the CAN bit time and the number of sample points. Nominal Bit Time / Bit Interval SYNC_SEG PROP_SEGPHASE_SEG 1 PHASE_SEG2 = 1 T q (Time Quantum): Smallest time unit defined by the CAN protocol; derived from the System Oscillator Period. SAMPLE POINT(S) SJW

© 2008, Renesas Technology America, Inc., All Rights Reserved 21 Pre-scaler, TEC, REC and COSTR CAN0 Baud Rate Pre-Scaler  Determines the T q time, which is used to build-up CAN bit timing CAN0 Transmit Error Counter (TEC)  Incremented/decremented in accordance with the CAN protocol CAN Receive Error Counter (REC)  Incremented/decremented in accordance with the CAN protocol CAN0 Time-Stamp Register (C0STR)  C0STR value is automatically stored into the message mailbox when a message is transmitted or received

© 2008, Renesas Technology America, Inc., All Rights Reserved 22 Interrupt Registers CAN0 Slot Interrupt Mask Register  Specifies whether a corresponding message mailbox will request or not request an interrupt. CAN0 Slot Interrupt Status Register  Shows which mailbox was the source of the interrupt. CAN0 Error Interrupt Mask Register  Enables / Disables interrupts: - Bus OFF - Error Passive -CAN BUS Error CAN0 Error Interrupt Status Register  Shows the source of the interrupt.

© 2008, Renesas Technology America, Inc., All Rights Reserved 23 CAN0 Global Mask Registers  C0GMR0  C0GMR1  C0GMR2  C0GMR3  C0GMR4 If a bit is set to ‘1’, then the corresponding bit in the received message is checked. If a bit is cleared to ‘0’, then the corresponding bit in the received message is not checked. For example: - If Global Mask Registers = all ‘0’, messages with any ID will be accepted. - If Global Mask Registers = all ‘1’, only messages with the exact ID of the mailbox will be accepted. CAN0 Local Mask Register A and B  C0LMAR0 - C0LMAR4  C0LMBR0 - C0LMBR4 --- STD ID10 STD ID9 STD ID8 STD ID7 STD ID6 -- STD ID5 STD ID4 STD ID3 STD ID2 STD ID1 STD ID EXT ID17 EXT ID16 EXT ID15 EXT ID14 EXT ID13 EXT ID12 EXT ID11 EXT ID10 EXT ID9 EXT ID8 EXT ID7 EXT ID6 -- EXT ID5 EXT ID4 EXT ID3 EXT ID2 EXT ID1 EXT ID0 Global/Local Mask Registers Operate on Mailboxes 0 to 13 Operate on Mailbox 14 Operate on Mailbox 15

© 2008, Renesas Technology America, Inc., All Rights Reserved 24 Slot Control Register CAN0 Message Slot Control Register  Used to indicate or select –CAN module has Transmitted / Received a message. –CAN module is in the process of Transmitting / Receiving a message. –Message Lost / Message Overrun. –Can module has Transmitted / Received a Remote Frame. –Automatic answering of Remote Frames. –Acceptance of Remote Frames / Data Frames. –Transmit / Receive Message Enable

© 2008, Renesas Technology America, Inc., All Rights Reserved 25 Buffer Registers CAN0 Slot Buffer Select Register  Mailbox and Buffer Slot is selected via this 8-bit register. CAN0 Message Slot Buffer Registers, 0 and 1  CAN0 Message Slot Buffer (0 / 1) Standard ID0  CAN0 Message Slot Buffer (0 / 1) Standard ID1  CAN0 Message Slot Buffer (0 / 1) Extended ID0  CAN0 Message Slot Buffer (0 / 1) Extended ID1  CAN0 Message Slot Buffer (0 / 1) Extended ID2  CAN0 Message Slot Buffer (0 / 1) Data Length Code  CAN0 Message Slot Buffer (0 / 1) Data 0 to 7.  CAN0 Message Slot Buffer (0 / 1) Time Stamp High  CAN0 Message Slot Buffer (0 / 1) Time Stamp Low MB8MB4MB2MB1MB8MB4MB2MB1 SLOT BUFFER 1SLOT BUFFER 0 Example : Access Mailbox 0 via Buffer : Access Mailbox 5 via Buffer 1

© 2008, Renesas Technology America, Inc., All Rights Reserved 27 Course Summary  Intelligent I/O  DMAC II  X-Y converter  CAN