Embedded System Lab. Jung Young Jin The Design and Implementation of a Log-Structured File System D. Ma, J. Feng, and G. Li. LazyFTL: a page-level flash translation layer optimized for NAND flash memory. In Proceedings of the 2011 international conference on Management of data (SIGMOD’11), pages 1–12, 2011.

정 영 진 Embedded System Lab. FTL Introduction LazyFTL architecture Major functionalities State transition Performance evaluation Conclusion Reference Contents

정 영 진 Embedded System Lab. FTL FTL(Flash Translation Layer)  Flash memory disadvantage Operation unit  R/W : Page  Erase : Block Out-place-update Limited lifespan  Mapping Page Block Hybrid  Garbage Collection Full merge Partial merge Switch merge  Wear leveling

정 영 진 Embedded System Lab. Floating gate  Limited lifespan  Oxide wear FTL Drain Source Oxide Floating Gate Control Gate

정 영 진 Embedded System Lab. Kinds of Flash Memory  Bit count in flash memory cell  1bit(SLC) / 2bit(MLC) / 3bit(TLC) / 4bit(QLC)  Voltage ex) SLC : 100%(0), 0%(1) MLC : 100%(00), 66%(01), 33%(10), 0%(11)  Bit count increase: lifespan, stability, performance ↓ degree of integration ↑ FTL

정 영 진 Embedded System Lab. FTL HDD HDD?

정 영 진 Embedded System Lab. Page mapping FTL  Page-level mapping  Advantage Good performance compared to other mapping policy Random write  Disadvantage Large size mapping table FTL …… n x m LPNPPN ……… page 0 page 1 page 2 page 3 … page m … Block 0Block 1Block n Write 1(300) … … …… n x m … … …… n x m

정 영 진 Embedded System Lab. Block mapping FTL  Block-level mapping  Same page index in a block  Advantage Small size mapping table Sequential write  Disadvantage Random write FTL LBNPBN … …… page 0 page 1 page 2 page 3 … page m … Block 0Block 1Block n …… nn Write 66(300) LBN = 66/64 = 1 Offset = … …… …… nn

정 영 진 Embedded System Lab. Hybrid mapping FTL  Page-level and Block-level mapping  Different page index in a block  FAST, LAST, SAST, KAST… FTL LBNPBN …… nn Write 66(300) LBN = 66/64 = 1 Offset = 2 … … … … Block 0Block 1Block 100(Log Block) … … … …… DataLog Logical Page Offset Physical Page Offset …… ……… …… nn ……

정 영 진 Embedded System Lab. Garbage Collection  Make free page  Merge Full merge Partial merge Switch merge FTL erase change erase change erase change invalid valid free

정 영 진 Embedded System Lab. Wear leveling  Extend the life of Flash memory cell  Erase distribution FTL Block # Erase # … Block # Erase # …

정 영 진 Embedded System Lab. Overview of FTL  Page-level FTL scheme DFTL  Block-level FTL scheme NFTL-1. NFTL-N  Hybrid FTL scheme BAST, FAST, SAST, LAST, A-SAST, KAST, HFTL  Variable-length FTL μ-FTL, JFTL Introduction

정 영 진 Embedded System Lab. LazyFTL design principle  Page mapping FTL  2 bit map Update flag, invalidate flag  No wear-leveling Focus on address translation and data organization  LRU strategy in SRAM  Using lazy manner  Divide the entire flash memory into four parts Introduction

정 영 진 Embedded System Lab. Architecture of LazyFTL LazyFTL architecture

정 영 진 Embedded System Lab. Convert  CBA and the UBA cannot be too large  Convert the victim block to a normal data block logically  Only overhead for GMT updates  Convert operation four steps Select a victim block in UMT Collect mapping entries in UMT(update flag → 0) Modify mapping entries Victim block is converted to a normal data block logically Major functionalities

정 영 진 Embedded System Lab. Garbage collection  Valid pages should be relatively colder than the invalid ones Major functionalities

정 영 진 Embedded System Lab. Write  Simpler than the convert operation and the garbage collection operation. Major functionalities

정 영 진 Embedded System Lab. State transition of pages State transition

정 영 진 Embedded System Lab. State transition of pages Performance evaluation GMTUMT DBA CBA/UBA vailid page invailid page

정 영 진 Embedded System Lab. Experimental setup  1GB SLC flash memory(widely used, enterprise grade)  Trace-driven simulator, 36 qualified traces  Utilization 0%~82.87%  Compare with NFTL-1, NFTL-N, BAST, FAST, LAST, A-SAST (Block mapping FTL, Hybrid mapping FTL) Greedy strategy GC LBA size(Hybrid FTL) is same with UBA + CBA Performance evaluation

정 영 진 Embedded System Lab. Performance evaluation

정 영 진 Embedded System Lab. Performance evaluation

정 영 진 Embedded System Lab. LazyFTL successfully avoids merge operations LazyFTL is the most efficient and effective FTL scheme ever invented, which is hard to surpass since we have successfully approached the theoretically optimal result. Conclusion

정 영 진 Embedded System Lab. H.KimandS.Ahn.BPLRU:ABufferManagementSchemefor Improving Random Writes in Flash Storage. In FAST, S.-W. Lee, D.-J. Park, T.-S. Chung, et al. A Log Buffer Based Flash Translation Layer using Fully Associative Sector Translation. ACM Transactions on Embedded Computing Systems (TECS), 6(3), July Reference

정 영 진 Embedded System Lab. Q & A